iop_sw_cfg_defs.h

Axis 221 camera embedded programing interface

#ifndef __iop_sw_cfg_defs_h
#define __iop_sw_cfg_defs_h

/*
 * This file is autogenerated from
 *   file:           iop_sw_cfg.r
 * 
 *   by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_cfg_defs.h iop_sw_cfg.r
 * Any changes here will be lost.
 *
 * -*- buffer-read-only: t -*-
 */
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
  REG_READ( reg_##scope##_##reg, \
            (inst) + REG_RD_ADDR_##scope##_##reg )
#endif

#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
  REG_WRITE( reg_##scope##_##reg, \
             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif

#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
  REG_READ( reg_##scope##_##reg, \
            (inst) + REG_RD_ADDR_##scope##_##reg + \
	    (index) * STRIDE_##scope##_##reg )
#endif

#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
  REG_WRITE( reg_##scope##_##reg, \
             (inst) + REG_WR_ADDR_##scope##_##reg + \
	     (index) * STRIDE_##scope##_##reg, (val) )
#endif

#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif

#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif

#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
	    (index) * STRIDE_##scope##_##reg )
#endif

#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
	     (index) * STRIDE_##scope##_##reg, (val) )
#endif

#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif

#ifndef reg_page_size
#define reg_page_size 8192
#endif

#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
  ( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif

#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
    (index) * STRIDE_##scope##_##reg )
#endif

/* C-code for register scope iop_sw_cfg */

/* Register rw_crc_par_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_crc_par_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par_owner 0
#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par_owner 0

/* Register rw_dmc_in_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_dmc_in_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in_owner 4
#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in_owner 4

/* Register rw_dmc_out_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_dmc_out_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out_owner 8
#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out_owner 8

/* Register rw_fifo_in_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_fifo_in_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in_owner 12
#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in_owner 12

/* Register rw_fifo_in_extra_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_fifo_in_extra_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in_extra_owner 16
#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in_extra_owner 16

/* Register rw_fifo_out_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_fifo_out_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out_owner 20
#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out_owner 20

/* Register rw_fifo_out_extra_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_fifo_out_extra_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out_extra_owner 24
#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out_extra_owner 24

/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_sap_in_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_sap_in_owner 28
#define REG_WR_ADDR_iop_sw_cfg_rw_sap_in_owner 28

/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_sap_out_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_sap_out_owner 32
#define REG_WR_ADDR_iop_sw_cfg_rw_sap_out_owner 32

/* Register rw_scrc_in_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_scrc_in_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in_owner 36
#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in_owner 36

/* Register rw_scrc_out_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_scrc_out_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out_owner 40
#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out_owner 40

/* Register rw_spu_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 1;
  unsigned int dummy1 : 31;
} reg_iop_sw_cfg_rw_spu_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_spu_owner 44
#define REG_WR_ADDR_iop_sw_cfg_rw_spu_owner 44

/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_timer_grp0_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_owner 48
#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_owner 48

/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_timer_grp1_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_owner 52
#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_owner 52

/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_trigger_grp0_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 56
#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 56

/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_trigger_grp1_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 60
#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 60

/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_trigger_grp2_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 64
#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 64

/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_trigger_grp3_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 68
#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 68

/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_trigger_grp4_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 72
#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 72

/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_trigger_grp5_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 76
#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 76

/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_trigger_grp6_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 80
#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 80

/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_trigger_grp7_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 84
#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 84

/* Register rw_bus_mask, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int byte0 : 8;
  unsigned int byte1 : 8;
  unsigned int byte2 : 8;
  unsigned int byte3 : 8;
} reg_iop_sw_cfg_rw_bus_mask;
#define REG_RD_ADDR_iop_sw_cfg_rw_bus_mask 88
#define REG_WR_ADDR_iop_sw_cfg_rw_bus_mask 88

/* Register rw_bus_oe_mask, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int byte0 : 1;
  unsigned int byte1 : 1;
  unsigned int byte2 : 1;
  unsigned int byte3 : 1;
  unsigned int dummy1 : 28;
} reg_iop_sw_cfg_rw_bus_oe_mask;
#define REG_RD_ADDR_iop_sw_cfg_rw_bus_oe_mask 92
#define REG_WR_ADDR_iop_sw_cfg_rw_bus_oe_mask 92

/* Register rw_gio_mask, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int val : 32;
} reg_iop_sw_cfg_rw_gio_mask;
#define REG_RD_ADDR_iop_sw_cfg_rw_gio_mask 96
#define REG_WR_ADDR_iop_sw_cfg_rw_gio_mask 96

/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int val : 32;
} reg_iop_sw_cfg_rw_gio_oe_mask;
#define REG_RD_ADDR_iop_sw_cfg_rw_gio_oe_mask 100
#define REG_WR_ADDR_iop_sw_cfg_rw_gio_oe_mask 100

/* Register rw_pinmapping, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int bus_byte0 : 2;
  unsigned int bus_byte1 : 2;
  unsigned int bus_byte2 : 2;
  unsigned int bus_byte3 : 2;
  unsigned int gio3_0    : 2;
  unsigned int gio7_4    : 2;
  unsigned int gio11_8   : 2;
  unsigned int gio15_12  : 2;
  unsigned int gio19_16  : 2;
  unsigned int gio23_20  : 2;
  unsigned int gio27_24  : 2;
  unsigned int gio31_28  : 2;
  unsigned int dummy1    : 8;
} reg_iop_sw_cfg_rw_pinmapping;
#define REG_RD_ADDR_iop_sw_cfg_rw_pinmapping 104
#define REG_WR_ADDR_iop_sw_cfg_rw_pinmapping 104

/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int bus_lo    : 2;
  unsigned int bus_hi    : 2;
  unsigned int bus_lo_oe : 2;
  unsigned int bus_hi_oe : 2;
  unsigned int dummy1    : 24;
} reg_iop_sw_cfg_rw_bus_out_cfg;
#define REG_RD_ADDR_iop_sw_cfg_rw_bus_out_cfg 108
#define REG_WR_ADDR_iop_sw_cfg_rw_bus_out_cfg 108

/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int gio0    : 3;
  unsigned int gio0_oe : 1;
  unsigned int gio1    : 3;
  unsigned int gio1_oe : 1;
  unsigned int gio2    : 3;
  unsigned int gio2_oe : 1;
  unsigned int gio3    : 3;
  unsigned int gio3_oe : 1;
  unsigned int dummy1  : 16;
} reg_iop_sw_cfg_rw_gio_out_grp0_cfg;
#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 112
#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 112

/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int gio4    : 3;
  unsigned int gio4_oe : 1;
  unsigned int gio5    : 3;
  unsigned int gio5_oe : 1;
  unsigned int gio6    : 3;
  unsigned int gio6_oe : 1;
  unsigned int gio7    : 3;
  unsigned int gio7_oe : 1;
  unsigned int dummy1  : 16;
} reg_iop_sw_cfg_rw_gio_out_grp1_cfg;
#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 116
#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 116

/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int gio8     : 3;
  unsigned int gio8_oe  : 1;
  unsigned int gio9     : 3;
  unsigned int gio9_oe  : 1;
  unsigned int gio10    : 3;
  unsigned int gio10_oe : 1;
  unsigned int gio11    : 3;