iop_sw_cpu_defs_asm.h

Axis 221 camera embedded programing interface

#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___bit 10
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___lsb 11
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___bit 11
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___lsb 12
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___bit 12
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___lsb 13
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___bit 13
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___lsb 14
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___bit 14
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___lsb 15
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___bit 15
#define reg_iop_sw_cpu_rw_ack_intr1_offset 96

/* Register r_intr1, scope iop_sw_cpu, type r */
#define reg_iop_sw_cpu_r_intr1___mpu_16___lsb 0
#define reg_iop_sw_cpu_r_intr1___mpu_16___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_16___bit 0
#define reg_iop_sw_cpu_r_intr1___mpu_17___lsb 1
#define reg_iop_sw_cpu_r_intr1___mpu_17___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_17___bit 1
#define reg_iop_sw_cpu_r_intr1___mpu_18___lsb 2
#define reg_iop_sw_cpu_r_intr1___mpu_18___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_18___bit 2
#define reg_iop_sw_cpu_r_intr1___mpu_19___lsb 3
#define reg_iop_sw_cpu_r_intr1___mpu_19___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_19___bit 3
#define reg_iop_sw_cpu_r_intr1___mpu_20___lsb 4
#define reg_iop_sw_cpu_r_intr1___mpu_20___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_20___bit 4
#define reg_iop_sw_cpu_r_intr1___mpu_21___lsb 5
#define reg_iop_sw_cpu_r_intr1___mpu_21___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_21___bit 5
#define reg_iop_sw_cpu_r_intr1___mpu_22___lsb 6
#define reg_iop_sw_cpu_r_intr1___mpu_22___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_22___bit 6
#define reg_iop_sw_cpu_r_intr1___mpu_23___lsb 7
#define reg_iop_sw_cpu_r_intr1___mpu_23___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_23___bit 7
#define reg_iop_sw_cpu_r_intr1___mpu_24___lsb 8
#define reg_iop_sw_cpu_r_intr1___mpu_24___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_24___bit 8
#define reg_iop_sw_cpu_r_intr1___mpu_25___lsb 9
#define reg_iop_sw_cpu_r_intr1___mpu_25___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_25___bit 9
#define reg_iop_sw_cpu_r_intr1___mpu_26___lsb 10
#define reg_iop_sw_cpu_r_intr1___mpu_26___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_26___bit 10
#define reg_iop_sw_cpu_r_intr1___mpu_27___lsb 11
#define reg_iop_sw_cpu_r_intr1___mpu_27___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_27___bit 11
#define reg_iop_sw_cpu_r_intr1___mpu_28___lsb 12
#define reg_iop_sw_cpu_r_intr1___mpu_28___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_28___bit 12
#define reg_iop_sw_cpu_r_intr1___mpu_29___lsb 13
#define reg_iop_sw_cpu_r_intr1___mpu_29___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_29___bit 13
#define reg_iop_sw_cpu_r_intr1___mpu_30___lsb 14
#define reg_iop_sw_cpu_r_intr1___mpu_30___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_30___bit 14
#define reg_iop_sw_cpu_r_intr1___mpu_31___lsb 15
#define reg_iop_sw_cpu_r_intr1___mpu_31___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_31___bit 15
#define reg_iop_sw_cpu_r_intr1___dmc_in___lsb 16
#define reg_iop_sw_cpu_r_intr1___dmc_in___width 1
#define reg_iop_sw_cpu_r_intr1___dmc_in___bit 16
#define reg_iop_sw_cpu_r_intr1___dmc_out___lsb 17
#define reg_iop_sw_cpu_r_intr1___dmc_out___width 1
#define reg_iop_sw_cpu_r_intr1___dmc_out___bit 17
#define reg_iop_sw_cpu_r_intr1___fifo_in___lsb 18
#define reg_iop_sw_cpu_r_intr1___fifo_in___width 1
#define reg_iop_sw_cpu_r_intr1___fifo_in___bit 18
#define reg_iop_sw_cpu_r_intr1___fifo_out___lsb 19
#define reg_iop_sw_cpu_r_intr1___fifo_out___width 1
#define reg_iop_sw_cpu_r_intr1___fifo_out___bit 19
#define reg_iop_sw_cpu_r_intr1___fifo_in_extra___lsb 20
#define reg_iop_sw_cpu_r_intr1___fifo_in_extra___width 1
#define reg_iop_sw_cpu_r_intr1___fifo_in_extra___bit 20
#define reg_iop_sw_cpu_r_intr1___fifo_out_extra___lsb 21
#define reg_iop_sw_cpu_r_intr1___fifo_out_extra___width 1
#define reg_iop_sw_cpu_r_intr1___fifo_out_extra___bit 21
#define reg_iop_sw_cpu_r_intr1___trigger_grp0___lsb 22
#define reg_iop_sw_cpu_r_intr1___trigger_grp0___width 1
#define reg_iop_sw_cpu_r_intr1___trigger_grp0___bit 22
#define reg_iop_sw_cpu_r_intr1___trigger_grp1___lsb 23
#define reg_iop_sw_cpu_r_intr1___trigger_grp1___width 1
#define reg_iop_sw_cpu_r_intr1___trigger_grp1___bit 23
#define reg_iop_sw_cpu_r_intr1___trigger_grp2___lsb 24
#define reg_iop_sw_cpu_r_intr1___trigger_grp2___width 1
#define reg_iop_sw_cpu_r_intr1___trigger_grp2___bit 24
#define reg_iop_sw_cpu_r_intr1___trigger_grp3___lsb 25
#define reg_iop_sw_cpu_r_intr1___trigger_grp3___width 1
#define reg_iop_sw_cpu_r_intr1___trigger_grp3___bit 25
#define reg_iop_sw_cpu_r_intr1___trigger_grp4___lsb 26
#define reg_iop_sw_cpu_r_intr1___trigger_grp4___width 1
#define reg_iop_sw_cpu_r_intr1___trigger_grp4___bit 26
#define reg_iop_sw_cpu_r_intr1___trigger_grp5___lsb 27
#define reg_iop_sw_cpu_r_intr1___trigger_grp5___width 1
#define reg_iop_sw_cpu_r_intr1___trigger_grp5___bit 27
#define reg_iop_sw_cpu_r_intr1___trigger_grp6___lsb 28
#define reg_iop_sw_cpu_r_intr1___trigger_grp6___width 1
#define reg_iop_sw_cpu_r_intr1___trigger_grp6___bit 28
#define reg_iop_sw_cpu_r_intr1___trigger_grp7___lsb 29
#define reg_iop_sw_cpu_r_intr1___trigger_grp7___width 1
#define reg_iop_sw_cpu_r_intr1___trigger_grp7___bit 29
#define reg_iop_sw_cpu_r_intr1___timer_grp0___lsb 30
#define reg_iop_sw_cpu_r_intr1___timer_grp0___width 1
#define reg_iop_sw_cpu_r_intr1___timer_grp0___bit 30
#define reg_iop_sw_cpu_r_intr1___timer_grp1___lsb 31
#define reg_iop_sw_cpu_r_intr1___timer_grp1___width 1
#define reg_iop_sw_cpu_r_intr1___timer_grp1___bit 31
#define reg_iop_sw_cpu_r_intr1_offset 100

/* Register r_masked_intr1, scope iop_sw_cpu, type r */
#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___lsb 0
#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___bit 0
#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___lsb 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___bit 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___lsb 2
#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___bit 2
#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___lsb 3
#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___bit 3
#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___lsb 4
#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___bit 4
#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___lsb 5
#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___bit 5
#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___lsb 6
#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___bit 6
#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___lsb 7
#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___bit 7
#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___lsb 8
#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___bit 8
#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___lsb 9
#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___bit 9
#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___lsb 10
#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___bit 10
#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___lsb 11
#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___bit 11
#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___lsb 12
#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___bit 12
#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___lsb 13
#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___bit 13
#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___lsb 14
#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___bit 14
#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___lsb 15
#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___bit 15
#define reg_iop_sw_cpu_r_masked_intr1___dmc_in___lsb 16
#define reg_iop_sw_cpu_r_masked_intr1___dmc_in___width 1
#define reg_iop_sw_cpu_r_masked_intr1___dmc_in___bit 16
#define reg_iop_sw_cpu_r_masked_intr1___dmc_out___lsb 17
#define reg_iop_sw_cpu_r_masked_intr1___dmc_out___width 1
#define reg_iop_sw_cpu_r_masked_intr1___dmc_out___bit 17
#define reg_iop_sw_cpu_r_masked_intr1___fifo_in___lsb 18
#define reg_iop_sw_cpu_r_masked_intr1___fifo_in___width 1
#define reg_iop_sw_cpu_r_masked_intr1___fifo_in___bit 18
#define reg_iop_sw_cpu_r_masked_intr1___fifo_out___lsb 19
#define reg_iop_sw_cpu_r_masked_intr1___fifo_out___width 1
#define reg_iop_sw_cpu_r_masked_intr1___fifo_out___bit 19
#define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___lsb 20
#define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___width 1
#define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___bit 20
#define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___lsb 21
#define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___width 1
#define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___bit 21
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___lsb 22
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___width 1
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___bit 22
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___lsb 23
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___width 1
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___bit 23
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___lsb 24
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___width 1
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___bit 24
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___lsb 25
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___width 1
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___bit 25
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___lsb 26
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___width 1
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___bit 26
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___lsb 27
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___width 1
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___bit 27
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___lsb 28
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___width 1
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___bit 28
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___lsb 29
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___width 1
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___bit 29
#define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___lsb 30
#define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___width 1
#define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___bit 30
#define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___lsb 31
#define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___width 1
#define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___bit 31
#define reg_iop_sw_cpu_r_masked_intr1_offset 104


/* Constants */
#define regk_iop_sw_cpu_copy                      0x00000000
#define regk_iop_sw_cpu_no                        0x00000000
#define regk_iop_sw_cpu_rd                        0x00000002
#define regk_iop_sw_cpu_reg_copy                  0x00000001
#define regk_iop_sw_cpu_rw_bus_clr_mask_default   0x00000000
#define regk_iop_sw_cpu_rw_bus_oe_clr_mask_default  0x00000000
#define regk_iop_sw_cpu_rw_bus_oe_set_mask_default  0x00000000
#define regk_iop_sw_cpu_rw_bus_set_mask_default   0x00000000
#define regk_iop_sw_cpu_rw_gio_clr_mask_default   0x00000000
#define regk_iop_sw_cpu_rw_gio_oe_clr_mask_default  0x00000000
#define regk_iop_sw_cpu_rw_gio_oe_set_mask_default  0x00000000
#define regk_iop_sw_cpu_rw_gio_set_mask_default   0x00000000
#define regk_iop_sw_cpu_rw_intr0_mask_default     0x00000000
#define regk_iop_sw_cpu_rw_intr1_mask_default     0x00000000
#define regk_iop_sw_cpu_wr                        0x00000003
#define regk_iop_sw_cpu_yes                       0x00000001
#endif /* __iop_sw_cpu_defs_asm_h */