iop_sw_mpu_defs_asm.h

Axis 221 camera embedded programing interface

#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___lsb 13
#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___bit 13
#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___lsb 14
#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___bit 14
#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___lsb 15
#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___bit 15
#define reg_iop_sw_mpu_r_masked_intr_grp0_offset 96

/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */
#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___lsb 0
#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___bit 0
#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___lsb 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___bit 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___lsb 2
#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___bit 2
#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___lsb 3
#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___bit 3
#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___lsb 4
#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___bit 4
#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___lsb 5
#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___bit 5
#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___lsb 6
#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___bit 6
#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___lsb 7
#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___bit 7
#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___lsb 8
#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___bit 8
#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___lsb 9
#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___bit 9
#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___lsb 10
#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___bit 10
#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___lsb 11
#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___bit 11
#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___lsb 12
#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___bit 12
#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___lsb 13
#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___bit 13
#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___lsb 14
#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___bit 14
#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___lsb 15
#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___bit 15
#define reg_iop_sw_mpu_rw_intr_grp1_mask_offset 100

/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */
#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___lsb 0
#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___width 1
#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___bit 0
#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___lsb 4
#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___width 1
#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___bit 4
#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___lsb 8
#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___width 1
#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___bit 8
#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___lsb 12
#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___width 1
#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___bit 12
#define reg_iop_sw_mpu_rw_ack_intr_grp1_offset 104

/* Register r_intr_grp1, scope iop_sw_mpu, type r */
#define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___lsb 0
#define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___width 1
#define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___bit 0
#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___lsb 1
#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___width 1
#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___bit 1
#define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___lsb 2
#define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___width 1
#define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___bit 2
#define reg_iop_sw_mpu_r_intr_grp1___dmc_out___lsb 3
#define reg_iop_sw_mpu_r_intr_grp1___dmc_out___width 1
#define reg_iop_sw_mpu_r_intr_grp1___dmc_out___bit 3
#define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___lsb 4
#define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___width 1
#define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___bit 4
#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___lsb 5
#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___width 1
#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___bit 5
#define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___lsb 6
#define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___width 1
#define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___bit 6
#define reg_iop_sw_mpu_r_intr_grp1___dmc_in___lsb 7
#define reg_iop_sw_mpu_r_intr_grp1___dmc_in___width 1
#define reg_iop_sw_mpu_r_intr_grp1___dmc_in___bit 7
#define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___lsb 8
#define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___width 1
#define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___bit 8
#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___lsb 9
#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___width 1
#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___bit 9
#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___lsb 10
#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___width 1
#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___bit 10
#define reg_iop_sw_mpu_r_intr_grp1___fifo_out___lsb 11
#define reg_iop_sw_mpu_r_intr_grp1___fifo_out___width 1
#define reg_iop_sw_mpu_r_intr_grp1___fifo_out___bit 11
#define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___lsb 12
#define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___width 1
#define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___bit 12
#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___lsb 13
#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___width 1
#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___bit 13
#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___lsb 14
#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___width 1
#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___bit 14
#define reg_iop_sw_mpu_r_intr_grp1___fifo_in___lsb 15
#define reg_iop_sw_mpu_r_intr_grp1___fifo_in___width 1
#define reg_iop_sw_mpu_r_intr_grp1___fifo_in___bit 15
#define reg_iop_sw_mpu_r_intr_grp1_offset 108

/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */
#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___lsb 0
#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___bit 0
#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___lsb 1
#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___bit 1
#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___lsb 2
#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___bit 2
#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___lsb 3
#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___bit 3
#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___lsb 4
#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___bit 4
#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___lsb 5
#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___bit 5
#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___lsb 6
#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___bit 6
#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___lsb 7
#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___bit 7
#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___lsb 8
#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___bit 8
#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___lsb 9
#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___bit 9
#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___lsb 10
#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___bit 10
#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___lsb 11
#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___bit 11
#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___lsb 12
#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___bit 12
#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___lsb 13
#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___bit 13
#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___lsb 14
#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___bit 14
#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___lsb 15
#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___bit 15
#define reg_iop_sw_mpu_r_masked_intr_grp1_offset 112

/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */
#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___lsb 0
#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___width 1
#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___bit 0
#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___lsb 1
#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___width 1
#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___bit 1
#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___lsb 2
#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___width 1
#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___bit 2
#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___lsb 3
#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___width 1
#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___bit 3
#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___lsb 4
#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___width 1
#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___bit 4
#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___lsb 5
#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___width 1
#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___bit 5
#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___lsb 6
#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___width 1
#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___bit 6
#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___lsb 7
#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___width 1
#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___bit 7
#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___lsb 8
#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___width 1
#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___bit 8
#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___lsb 9
#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___width 1
#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___bit 9
#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___lsb 10
#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___width 1
#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___bit 10
#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___lsb 11
#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___width 1
#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___bit 11
#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___lsb 12
#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___width 1
#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___bit 12
#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___lsb 13
#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___width 1
#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___bit 13
#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___lsb 14
#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___width 1
#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___bit 14
#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___lsb 15
#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___width 1
#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___bit 15
#define reg_iop_sw_mpu_rw_intr_grp2_mask_offset 116

/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */
#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___lsb 0
#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___width 1
#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___bit 0
#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___lsb 4
#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___width 1
#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___bit 4
#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___lsb 8
#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___width 1
#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___bit 8
#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___lsb 12
#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___width 1
#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___bit 12
#define reg_iop_sw_mpu_rw_ack_intr_grp2_offset 120

/* Register r_intr_grp2, scope iop_sw_mpu, type r */
#define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___lsb 0
#define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___width 1
#define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___bit 0
#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___lsb 1
#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___width 1
#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___bit 1
#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___lsb 2
#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___width 1
#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___bit 2
#define reg_iop_sw_mpu_r_intr_grp2___fifo_out___lsb 3
#define reg_iop_sw_mpu_r_intr_grp2___fifo_out___width 1
#define reg_iop_sw_mpu_r_intr_grp2___fifo_out___bit 3
#define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___lsb 4
#define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___width 1
#define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___bit 4
#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___lsb 5
#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___width 1
#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___bit 5
#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___lsb 6
#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___width 1
#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___bit 6
#define reg_iop_sw_mpu_r_intr_grp2___fifo_in___lsb 7
#define reg_iop_sw_mpu_r_intr_grp2___fifo_in___width 1
#define reg_iop_sw_mpu_r_intr_grp2___fifo_in___bit 7
#define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___lsb 8
#define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___width 1