iop_sw_mpu_defs_asm.h

Axis 221 camera embedded programing interface

#define reg_iop_sw_mpu_rw_cpu_intr___intr27___width 1
#define reg_iop_sw_mpu_rw_cpu_intr___intr27___bit 27
#define reg_iop_sw_mpu_rw_cpu_intr___intr28___lsb 28
#define reg_iop_sw_mpu_rw_cpu_intr___intr28___width 1
#define reg_iop_sw_mpu_rw_cpu_intr___intr28___bit 28
#define reg_iop_sw_mpu_rw_cpu_intr___intr29___lsb 29
#define reg_iop_sw_mpu_rw_cpu_intr___intr29___width 1
#define reg_iop_sw_mpu_rw_cpu_intr___intr29___bit 29
#define reg_iop_sw_mpu_rw_cpu_intr___intr30___lsb 30
#define reg_iop_sw_mpu_rw_cpu_intr___intr30___width 1
#define reg_iop_sw_mpu_rw_cpu_intr___intr30___bit 30
#define reg_iop_sw_mpu_rw_cpu_intr___intr31___lsb 31
#define reg_iop_sw_mpu_rw_cpu_intr___intr31___width 1
#define reg_iop_sw_mpu_rw_cpu_intr___intr31___bit 31
#define reg_iop_sw_mpu_rw_cpu_intr_offset 76

/* Register r_cpu_intr, scope iop_sw_mpu, type r */
#define reg_iop_sw_mpu_r_cpu_intr___intr0___lsb 0
#define reg_iop_sw_mpu_r_cpu_intr___intr0___width 1
#define reg_iop_sw_mpu_r_cpu_intr___intr0___bit 0
#define reg_iop_sw_mpu_r_cpu_intr___intr1___lsb 1
#define reg_iop_sw_mpu_r_cpu_intr___intr1___width 1
#define reg_iop_sw_mpu_r_cpu_intr___intr1___bit 1
#define reg_iop_sw_mpu_r_cpu_intr___intr2___lsb 2
#define reg_iop_sw_mpu_r_cpu_intr___intr2___width 1
#define reg_iop_sw_mpu_r_cpu_intr___intr2___bit 2
#define reg_iop_sw_mpu_r_cpu_intr___intr3___lsb 3
#define reg_iop_sw_mpu_r_cpu_intr___intr3___width 1
#define reg_iop_sw_mpu_r_cpu_intr___intr3___bit 3
#define reg_iop_sw_mpu_r_cpu_intr___intr4___lsb 4
#define reg_iop_sw_mpu_r_cpu_intr___intr4___width 1
#define reg_iop_sw_mpu_r_cpu_intr___intr4___bit 4
#define reg_iop_sw_mpu_r_cpu_intr___intr5___lsb 5
#define reg_iop_sw_mpu_r_cpu_intr___intr5___width 1
#define reg_iop_sw_mpu_r_cpu_intr___intr5___bit 5
#define reg_iop_sw_mpu_r_cpu_intr___intr6___lsb 6
#define reg_iop_sw_mpu_r_cpu_intr___intr6___width 1
#define reg_iop_sw_mpu_r_cpu_intr___intr6___bit 6
#define reg_iop_sw_mpu_r_cpu_intr___intr7___lsb 7
#define reg_iop_sw_mpu_r_cpu_intr___intr7___width 1
#define reg_iop_sw_mpu_r_cpu_intr___intr7___bit 7
#define reg_iop_sw_mpu_r_cpu_intr___intr8___lsb 8
#define reg_iop_sw_mpu_r_cpu_intr___intr8___width 1
#define reg_iop_sw_mpu_r_cpu_intr___intr8___bit 8
#define reg_iop_sw_mpu_r_cpu_intr___intr9___lsb 9
#define reg_iop_sw_mpu_r_cpu_intr___intr9___width 1
#define reg_iop_sw_mpu_r_cpu_intr___intr9___bit 9
#define reg_iop_sw_mpu_r_cpu_intr___intr10___lsb 10
#define reg_iop_sw_mpu_r_cpu_intr___intr10___width 1
#define reg_iop_sw_mpu_r_cpu_intr___intr10___bit 10
#define reg_iop_sw_mpu_r_cpu_intr___intr11___lsb 11
#define reg_iop_sw_mpu_r_cpu_intr___intr11___width 1
#define reg_iop_sw_mpu_r_cpu_intr___intr11___bit 11
#define reg_iop_sw_mpu_r_cpu_intr___intr12___lsb 12
#define reg_iop_sw_mpu_r_cpu_intr___intr12___width 1
#define reg_iop_sw_mpu_r_cpu_intr___intr12___bit 12
#define reg_iop_sw_mpu_r_cpu_intr___intr13___lsb 13
#define reg_iop_sw_mpu_r_cpu_intr___intr13___width 1
#define reg_iop_sw_mpu_r_cpu_intr___intr13___bit 13
#define reg_iop_sw_mpu_r_cpu_intr___intr14___lsb 14
#define reg_iop_sw_mpu_r_cpu_intr___intr14___width 1
#define reg_iop_sw_mpu_r_cpu_intr___intr14___bit 14
#define reg_iop_sw_mpu_r_cpu_intr___intr15___lsb 15
#define reg_iop_sw_mpu_r_cpu_intr___intr15___width 1
#define reg_iop_sw_mpu_r_cpu_intr___intr15___bit 15
#define reg_iop_sw_mpu_r_cpu_intr___intr16___lsb 16
#define reg_iop_sw_mpu_r_cpu_intr___intr16___width 1
#define reg_iop_sw_mpu_r_cpu_intr___intr16___bit 16
#define reg_iop_sw_mpu_r_cpu_intr___intr17___lsb 17
#define reg_iop_sw_mpu_r_cpu_intr___intr17___width 1
#define reg_iop_sw_mpu_r_cpu_intr___intr17___bit 17
#define reg_iop_sw_mpu_r_cpu_intr___intr18___lsb 18
#define reg_iop_sw_mpu_r_cpu_intr___intr18___width 1
#define reg_iop_sw_mpu_r_cpu_intr___intr18___bit 18
#define reg_iop_sw_mpu_r_cpu_intr___intr19___lsb 19
#define reg_iop_sw_mpu_r_cpu_intr___intr19___width 1
#define reg_iop_sw_mpu_r_cpu_intr___intr19___bit 19
#define reg_iop_sw_mpu_r_cpu_intr___intr20___lsb 20
#define reg_iop_sw_mpu_r_cpu_intr___intr20___width 1
#define reg_iop_sw_mpu_r_cpu_intr___intr20___bit 20
#define reg_iop_sw_mpu_r_cpu_intr___intr21___lsb 21
#define reg_iop_sw_mpu_r_cpu_intr___intr21___width 1
#define reg_iop_sw_mpu_r_cpu_intr___intr21___bit 21
#define reg_iop_sw_mpu_r_cpu_intr___intr22___lsb 22
#define reg_iop_sw_mpu_r_cpu_intr___intr22___width 1
#define reg_iop_sw_mpu_r_cpu_intr___intr22___bit 22
#define reg_iop_sw_mpu_r_cpu_intr___intr23___lsb 23
#define reg_iop_sw_mpu_r_cpu_intr___intr23___width 1
#define reg_iop_sw_mpu_r_cpu_intr___intr23___bit 23
#define reg_iop_sw_mpu_r_cpu_intr___intr24___lsb 24
#define reg_iop_sw_mpu_r_cpu_intr___intr24___width 1
#define reg_iop_sw_mpu_r_cpu_intr___intr24___bit 24
#define reg_iop_sw_mpu_r_cpu_intr___intr25___lsb 25
#define reg_iop_sw_mpu_r_cpu_intr___intr25___width 1
#define reg_iop_sw_mpu_r_cpu_intr___intr25___bit 25
#define reg_iop_sw_mpu_r_cpu_intr___intr26___lsb 26
#define reg_iop_sw_mpu_r_cpu_intr___intr26___width 1
#define reg_iop_sw_mpu_r_cpu_intr___intr26___bit 26
#define reg_iop_sw_mpu_r_cpu_intr___intr27___lsb 27
#define reg_iop_sw_mpu_r_cpu_intr___intr27___width 1
#define reg_iop_sw_mpu_r_cpu_intr___intr27___bit 27
#define reg_iop_sw_mpu_r_cpu_intr___intr28___lsb 28
#define reg_iop_sw_mpu_r_cpu_intr___intr28___width 1
#define reg_iop_sw_mpu_r_cpu_intr___intr28___bit 28
#define reg_iop_sw_mpu_r_cpu_intr___intr29___lsb 29
#define reg_iop_sw_mpu_r_cpu_intr___intr29___width 1
#define reg_iop_sw_mpu_r_cpu_intr___intr29___bit 29
#define reg_iop_sw_mpu_r_cpu_intr___intr30___lsb 30
#define reg_iop_sw_mpu_r_cpu_intr___intr30___width 1
#define reg_iop_sw_mpu_r_cpu_intr___intr30___bit 30
#define reg_iop_sw_mpu_r_cpu_intr___intr31___lsb 31
#define reg_iop_sw_mpu_r_cpu_intr___intr31___width 1
#define reg_iop_sw_mpu_r_cpu_intr___intr31___bit 31
#define reg_iop_sw_mpu_r_cpu_intr_offset 80

/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */
#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___lsb 0
#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___width 1
#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___bit 0
#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___lsb 1
#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___width 1
#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___bit 1
#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___lsb 2
#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___width 1
#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___bit 2
#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___lsb 3
#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___width 1
#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___bit 3
#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___lsb 4
#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___width 1
#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___bit 4
#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___lsb 5
#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___width 1
#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___bit 5
#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___lsb 6
#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___width 1
#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___bit 6
#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___lsb 7
#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___width 1
#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___bit 7
#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___lsb 8
#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___width 1
#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___bit 8
#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___lsb 9
#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___width 1
#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___bit 9
#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___lsb 10
#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___width 1
#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___bit 10
#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___lsb 11
#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___width 1
#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___bit 11
#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___lsb 12
#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___width 1
#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___bit 12
#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___lsb 13
#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___width 1
#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___bit 13
#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___lsb 14
#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___width 1
#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___bit 14
#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___lsb 15
#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___width 1
#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___bit 15
#define reg_iop_sw_mpu_rw_intr_grp0_mask_offset 84

/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */
#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___lsb 0
#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___width 1
#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___bit 0
#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___lsb 4
#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___width 1
#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___bit 4
#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___lsb 8
#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___width 1
#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___bit 8
#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___lsb 12
#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___width 1
#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___bit 12
#define reg_iop_sw_mpu_rw_ack_intr_grp0_offset 88

/* Register r_intr_grp0, scope iop_sw_mpu, type r */
#define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___lsb 0
#define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___width 1
#define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___bit 0
#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___lsb 1
#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___width 1
#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___bit 1
#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___lsb 2
#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___width 1
#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___bit 2
#define reg_iop_sw_mpu_r_intr_grp0___fifo_out___lsb 3
#define reg_iop_sw_mpu_r_intr_grp0___fifo_out___width 1
#define reg_iop_sw_mpu_r_intr_grp0___fifo_out___bit 3
#define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___lsb 4
#define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___width 1
#define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___bit 4
#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___lsb 5
#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___width 1
#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___bit 5
#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___lsb 6
#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___width 1
#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___bit 6
#define reg_iop_sw_mpu_r_intr_grp0___fifo_in___lsb 7
#define reg_iop_sw_mpu_r_intr_grp0___fifo_in___width 1
#define reg_iop_sw_mpu_r_intr_grp0___fifo_in___bit 7
#define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___lsb 8
#define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___width 1
#define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___bit 8
#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___lsb 9
#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___width 1
#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___bit 9
#define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___lsb 10
#define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___width 1
#define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___bit 10
#define reg_iop_sw_mpu_r_intr_grp0___dmc_out___lsb 11
#define reg_iop_sw_mpu_r_intr_grp0___dmc_out___width 1
#define reg_iop_sw_mpu_r_intr_grp0___dmc_out___bit 11
#define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___lsb 12
#define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___width 1
#define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___bit 12
#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___lsb 13
#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___width 1
#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___bit 13
#define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___lsb 14
#define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___width 1
#define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___bit 14
#define reg_iop_sw_mpu_r_intr_grp0___dmc_in___lsb 15
#define reg_iop_sw_mpu_r_intr_grp0___dmc_in___width 1
#define reg_iop_sw_mpu_r_intr_grp0___dmc_in___bit 15
#define reg_iop_sw_mpu_r_intr_grp0_offset 92

/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */
#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___lsb 0
#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___bit 0
#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___lsb 1
#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___bit 1
#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___lsb 2
#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___bit 2
#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___lsb 3
#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___bit 3
#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___lsb 4
#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___bit 4
#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___lsb 5
#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___bit 5
#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___lsb 6
#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___bit 6
#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___lsb 7
#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___bit 7
#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___lsb 8
#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___bit 8
#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___lsb 9
#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___bit 9
#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___lsb 10
#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___bit 10
#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___lsb 11
#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___bit 11
#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___lsb 12
#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___bit 12