iop_sw_cfg_defs_asm.h

Axis 221 camera embedded programing interface

#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___lsb 7
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___width 1
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___bit 7
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___lsb 8
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___width 1
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___bit 8
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___lsb 9
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___width 1
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___bit 9
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___lsb 10
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___width 1
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___bit 10
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___lsb 11
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___width 1
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___bit 11
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___lsb 12
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___width 1
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___bit 12
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___lsb 13
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___width 1
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___bit 13
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___lsb 14
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___width 1
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___bit 14
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___lsb 15
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___width 1
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___bit 15
#define reg_iop_sw_cfg_rw_trigger_grps_cfg_offset 156

/* Register rw_pdp_cfg, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_pdp_cfg___out_strb___lsb 0
#define reg_iop_sw_cfg_rw_pdp_cfg___out_strb___width 4
#define reg_iop_sw_cfg_rw_pdp_cfg___in_src___lsb 4
#define reg_iop_sw_cfg_rw_pdp_cfg___in_src___width 2
#define reg_iop_sw_cfg_rw_pdp_cfg___in_size___lsb 6
#define reg_iop_sw_cfg_rw_pdp_cfg___in_size___width 3
#define reg_iop_sw_cfg_rw_pdp_cfg___in_last___lsb 9
#define reg_iop_sw_cfg_rw_pdp_cfg___in_last___width 2
#define reg_iop_sw_cfg_rw_pdp_cfg___in_strb___lsb 11
#define reg_iop_sw_cfg_rw_pdp_cfg___in_strb___width 4
#define reg_iop_sw_cfg_rw_pdp_cfg_offset 160

/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out_strb___lsb 0
#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out_strb___width 3
#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_data___lsb 3
#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_data___width 3
#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_last___lsb 6
#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_last___width 2
#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_strb___lsb 8
#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_strb___width 3
#define reg_iop_sw_cfg_rw_sdp_cfg_offset 164


/* Constants */
#define regk_iop_sw_cfg_a                         0x00000001
#define regk_iop_sw_cfg_b                         0x00000002
#define regk_iop_sw_cfg_bus                       0x00000000
#define regk_iop_sw_cfg_bus_rot16                 0x00000002
#define regk_iop_sw_cfg_bus_rot24                 0x00000003
#define regk_iop_sw_cfg_bus_rot8                  0x00000001
#define regk_iop_sw_cfg_clk12                     0x00000000
#define regk_iop_sw_cfg_cpu                       0x00000000
#define regk_iop_sw_cfg_gated_clk0                0x0000000e
#define regk_iop_sw_cfg_gated_clk1                0x0000000f
#define regk_iop_sw_cfg_gio0                      0x00000004
#define regk_iop_sw_cfg_gio1                      0x00000001
#define regk_iop_sw_cfg_gio2                      0x00000005
#define regk_iop_sw_cfg_gio3                      0x00000002
#define regk_iop_sw_cfg_gio4                      0x00000006
#define regk_iop_sw_cfg_gio5                      0x00000003
#define regk_iop_sw_cfg_gio6                      0x00000007
#define regk_iop_sw_cfg_gio7                      0x00000004
#define regk_iop_sw_cfg_gio_in18                  0x00000002
#define regk_iop_sw_cfg_gio_in19                  0x00000003
#define regk_iop_sw_cfg_gio_in20                  0x00000004
#define regk_iop_sw_cfg_gio_in21                  0x00000005
#define regk_iop_sw_cfg_gio_in26                  0x00000006
#define regk_iop_sw_cfg_gio_in27                  0x00000007
#define regk_iop_sw_cfg_gio_in4                   0x00000000
#define regk_iop_sw_cfg_gio_in5                   0x00000001
#define regk_iop_sw_cfg_last_timer_grp0_tmr2      0x00000001
#define regk_iop_sw_cfg_last_timer_grp1_tmr2      0x00000002
#define regk_iop_sw_cfg_last_timer_grp1_tmr3      0x00000003
#define regk_iop_sw_cfg_mpu                       0x00000001
#define regk_iop_sw_cfg_none                      0x00000000
#define regk_iop_sw_cfg_pdp_out                   0x00000001
#define regk_iop_sw_cfg_pdp_out_hi                0x00000001
#define regk_iop_sw_cfg_pdp_out_lo                0x00000000
#define regk_iop_sw_cfg_rw_bus_mask_default       0x00000000
#define regk_iop_sw_cfg_rw_bus_oe_mask_default    0x00000000
#define regk_iop_sw_cfg_rw_bus_out_cfg_default    0x00000000
#define regk_iop_sw_cfg_rw_crc_par_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_dmc_in_owner_default   0x00000000
#define regk_iop_sw_cfg_rw_dmc_out_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_fifo_in_extra_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_fifo_in_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_fifo_out_extra_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_fifo_out_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_gio_mask_default       0x00000000
#define regk_iop_sw_cfg_rw_gio_oe_mask_default    0x00000000
#define regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default  0x00000000
#define regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default  0x00000000
#define regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default  0x00000000
#define regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default  0x00000000
#define regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default  0x00000000
#define regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default  0x00000000
#define regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default  0x00000000
#define regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default  0x00000000
#define regk_iop_sw_cfg_rw_pdp_cfg_default        0x00000000
#define regk_iop_sw_cfg_rw_pinmapping_default     0x00555555
#define regk_iop_sw_cfg_rw_sap_in_owner_default   0x00000000
#define regk_iop_sw_cfg_rw_sap_out_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_scrc_in_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_scrc_out_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_sdp_cfg_default        0x00000000
#define regk_iop_sw_cfg_rw_spu_cfg_default        0x00000000
#define regk_iop_sw_cfg_rw_spu_owner_default      0x00000000
#define regk_iop_sw_cfg_rw_timer_grp0_cfg_default  0x00000000
#define regk_iop_sw_cfg_rw_timer_grp0_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_timer_grp1_cfg_default  0x00000000
#define regk_iop_sw_cfg_rw_timer_grp1_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_trigger_grp0_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_trigger_grp1_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_trigger_grp2_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_trigger_grp3_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_trigger_grp4_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_trigger_grp5_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_trigger_grp6_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_trigger_grp7_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_trigger_grps_cfg_default  0x00000000
#define regk_iop_sw_cfg_sdp_out                   0x00000004
#define regk_iop_sw_cfg_size16                    0x00000002
#define regk_iop_sw_cfg_size24                    0x00000003
#define regk_iop_sw_cfg_size32                    0x00000004
#define regk_iop_sw_cfg_size8                     0x00000001
#define regk_iop_sw_cfg_spu                       0x00000002
#define regk_iop_sw_cfg_spu_bus_out0_hi           0x00000002
#define regk_iop_sw_cfg_spu_bus_out0_lo           0x00000002
#define regk_iop_sw_cfg_spu_bus_out1_hi           0x00000003
#define regk_iop_sw_cfg_spu_bus_out1_lo           0x00000003
#define regk_iop_sw_cfg_spu_g0                    0x00000007
#define regk_iop_sw_cfg_spu_g1                    0x00000007
#define regk_iop_sw_cfg_spu_g2                    0x00000007
#define regk_iop_sw_cfg_spu_g3                    0x00000007
#define regk_iop_sw_cfg_spu_g4                    0x00000007
#define regk_iop_sw_cfg_spu_g5                    0x00000007
#define regk_iop_sw_cfg_spu_g6                    0x00000007
#define regk_iop_sw_cfg_spu_g7                    0x00000007
#define regk_iop_sw_cfg_spu_gio0                  0x00000000
#define regk_iop_sw_cfg_spu_gio1                  0x00000001
#define regk_iop_sw_cfg_spu_gio5                  0x00000005
#define regk_iop_sw_cfg_spu_gio6                  0x00000006
#define regk_iop_sw_cfg_spu_gio7                  0x00000007
#define regk_iop_sw_cfg_spu_gio_out0              0x00000008
#define regk_iop_sw_cfg_spu_gio_out1              0x00000009
#define regk_iop_sw_cfg_spu_gio_out2              0x0000000a
#define regk_iop_sw_cfg_spu_gio_out3              0x0000000b
#define regk_iop_sw_cfg_spu_gio_out4              0x0000000c
#define regk_iop_sw_cfg_spu_gio_out5              0x0000000d
#define regk_iop_sw_cfg_spu_gio_out6              0x0000000e
#define regk_iop_sw_cfg_spu_gio_out7              0x0000000f
#define regk_iop_sw_cfg_spu_gioout0               0x00000000
#define regk_iop_sw_cfg_spu_gioout1               0x00000000
#define regk_iop_sw_cfg_spu_gioout10              0x00000007
#define regk_iop_sw_cfg_spu_gioout11              0x00000007
#define regk_iop_sw_cfg_spu_gioout12              0x00000007
#define regk_iop_sw_cfg_spu_gioout13              0x00000007
#define regk_iop_sw_cfg_spu_gioout14              0x00000007
#define regk_iop_sw_cfg_spu_gioout15              0x00000007
#define regk_iop_sw_cfg_spu_gioout16              0x00000007
#define regk_iop_sw_cfg_spu_gioout17              0x00000007
#define regk_iop_sw_cfg_spu_gioout18              0x00000007
#define regk_iop_sw_cfg_spu_gioout19              0x00000007
#define regk_iop_sw_cfg_spu_gioout2               0x00000001
#define regk_iop_sw_cfg_spu_gioout20              0x00000007
#define regk_iop_sw_cfg_spu_gioout21              0x00000007
#define regk_iop_sw_cfg_spu_gioout22              0x00000007
#define regk_iop_sw_cfg_spu_gioout23              0x00000007
#define regk_iop_sw_cfg_spu_gioout24              0x00000007
#define regk_iop_sw_cfg_spu_gioout25              0x00000007
#define regk_iop_sw_cfg_spu_gioout26              0x00000007
#define regk_iop_sw_cfg_spu_gioout27              0x00000007
#define regk_iop_sw_cfg_spu_gioout28              0x00000007
#define regk_iop_sw_cfg_spu_gioout29              0x00000007
#define regk_iop_sw_cfg_spu_gioout3               0x00000001
#define regk_iop_sw_cfg_spu_gioout30              0x00000007
#define regk_iop_sw_cfg_spu_gioout31              0x00000007
#define regk_iop_sw_cfg_spu_gioout4               0x00000002
#define regk_iop_sw_cfg_spu_gioout5               0x00000002
#define regk_iop_sw_cfg_spu_gioout6               0x00000003
#define regk_iop_sw_cfg_spu_gioout7               0x00000003
#define regk_iop_sw_cfg_spu_gioout8               0x00000007
#define regk_iop_sw_cfg_spu_gioout9               0x00000007
#define regk_iop_sw_cfg_strb_timer_grp0_tmr0      0x00000001
#define regk_iop_sw_cfg_strb_timer_grp0_tmr1      0x00000002
#define regk_iop_sw_cfg_strb_timer_grp1_tmr0      0x00000003
#define regk_iop_sw_cfg_strb_timer_grp1_tmr1      0x00000002
#define regk_iop_sw_cfg_timer_grp0                0x00000000
#define regk_iop_sw_cfg_timer_grp0_rot            0x00000001
#define regk_iop_sw_cfg_timer_grp0_strb0          0x00000005
#define regk_iop_sw_cfg_timer_grp0_strb1          0x00000005
#define regk_iop_sw_cfg_timer_grp0_strb2          0x00000005
#define regk_iop_sw_cfg_timer_grp0_strb3          0x00000005
#define regk_iop_sw_cfg_timer_grp0_tmr0           0x00000002
#define regk_iop_sw_cfg_timer_grp1                0x00000000
#define regk_iop_sw_cfg_timer_grp1_rot            0x00000001
#define regk_iop_sw_cfg_timer_grp1_strb0          0x00000006
#define regk_iop_sw_cfg_timer_grp1_strb1          0x00000006
#define regk_iop_sw_cfg_timer_grp1_strb2          0x00000006
#define regk_iop_sw_cfg_timer_grp1_strb3          0x00000006
#define regk_iop_sw_cfg_timer_grp1_tmr0           0x00000003
#define regk_iop_sw_cfg_trig0_0                   0x00000000
#define regk_iop_sw_cfg_trig0_1                   0x00000000
#define regk_iop_sw_cfg_trig0_2                   0x00000000
#define regk_iop_sw_cfg_trig0_3                   0x00000000
#define regk_iop_sw_cfg_trig1_0                   0x00000000
#define regk_iop_sw_cfg_trig1_1                   0x00000000
#define regk_iop_sw_cfg_trig1_2                   0x00000000
#define regk_iop_sw_cfg_trig1_3                   0x00000000
#define regk_iop_sw_cfg_trig2_0                   0x00000001
#define regk_iop_sw_cfg_trig2_1                   0x00000001
#define regk_iop_sw_cfg_trig2_2                   0x00000001
#define regk_iop_sw_cfg_trig2_3                   0x00000001
#define regk_iop_sw_cfg_trig3_0                   0x00000001
#define regk_iop_sw_cfg_trig3_1                   0x00000001
#define regk_iop_sw_cfg_trig3_2                   0x00000001
#define regk_iop_sw_cfg_trig3_3                   0x00000001
#define regk_iop_sw_cfg_trig4_0                   0x00000002
#define regk_iop_sw_cfg_trig4_1                   0x00000002
#define regk_iop_sw_cfg_trig4_2                   0x00000002
#define regk_iop_sw_cfg_trig4_3                   0x00000002
#define regk_iop_sw_cfg_trig5_0                   0x00000002
#define regk_iop_sw_cfg_trig5_1                   0x00000002
#define regk_iop_sw_cfg_trig5_2                   0x00000002
#define regk_iop_sw_cfg_trig5_3                   0x00000002
#define regk_iop_sw_cfg_trig6_0                   0x00000003
#define regk_iop_sw_cfg_trig6_1                   0x00000003
#define regk_iop_sw_cfg_trig6_2                   0x00000003
#define regk_iop_sw_cfg_trig6_3                   0x00000003
#define regk_iop_sw_cfg_trig7_0                   0x00000003
#define regk_iop_sw_cfg_trig7_1                   0x00000003
#define regk_iop_sw_cfg_trig7_2                   0x00000003
#define regk_iop_sw_cfg_trig7_3                   0x00000003
#endif /* __iop_sw_cfg_defs_asm_h */