iop_sw_cfg_defs_asm.h

Axis 221 camera embedded programing interface

#ifndef __iop_sw_cfg_defs_asm_h
#define __iop_sw_cfg_defs_asm_h

/*
 * This file is autogenerated from
 *   file:           iop_sw_cfg.r
 * 
 *   by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_cfg_defs_asm.h iop_sw_cfg.r
 * Any changes here will be lost.
 *
 * -*- buffer-read-only: t -*-
 */

#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif

#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif

#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif

#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif

#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif

#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif

#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
			 STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
                          ((inst) + offs + (index) * stride)
#endif

/* Register rw_crc_par_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_crc_par_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_crc_par_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_crc_par_owner_offset 0

/* Register rw_dmc_in_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_dmc_in_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_dmc_in_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_dmc_in_owner_offset 4

/* Register rw_dmc_out_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_dmc_out_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_dmc_out_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_dmc_out_owner_offset 8

/* Register rw_fifo_in_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_fifo_in_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_fifo_in_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_fifo_in_owner_offset 12

/* Register rw_fifo_in_extra_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_fifo_in_extra_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_fifo_in_extra_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_fifo_in_extra_owner_offset 16

/* Register rw_fifo_out_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_fifo_out_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_fifo_out_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_fifo_out_owner_offset 20

/* Register rw_fifo_out_extra_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_fifo_out_extra_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_fifo_out_extra_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_fifo_out_extra_owner_offset 24

/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_sap_in_owner_offset 28

/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_sap_out_owner_offset 32

/* Register rw_scrc_in_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_scrc_in_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_scrc_in_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_scrc_in_owner_offset 36

/* Register rw_scrc_out_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_scrc_out_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_scrc_out_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_scrc_out_owner_offset 40

/* Register rw_spu_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_spu_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_spu_owner___cfg___width 1
#define reg_iop_sw_cfg_rw_spu_owner___cfg___bit 0
#define reg_iop_sw_cfg_rw_spu_owner_offset 44

/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_timer_grp0_owner_offset 48

/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_timer_grp1_owner_offset 52

/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_trigger_grp0_owner_offset 56

/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_trigger_grp1_owner_offset 60

/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_trigger_grp2_owner_offset 64

/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_trigger_grp3_owner_offset 68

/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_trigger_grp4_owner_offset 72

/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_trigger_grp5_owner_offset 76

/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_trigger_grp6_owner_offset 80

/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_trigger_grp7_owner_offset 84

/* Register rw_bus_mask, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_bus_mask___byte0___lsb 0
#define reg_iop_sw_cfg_rw_bus_mask___byte0___width 8
#define reg_iop_sw_cfg_rw_bus_mask___byte1___lsb 8
#define reg_iop_sw_cfg_rw_bus_mask___byte1___width 8
#define reg_iop_sw_cfg_rw_bus_mask___byte2___lsb 16
#define reg_iop_sw_cfg_rw_bus_mask___byte2___width 8
#define reg_iop_sw_cfg_rw_bus_mask___byte3___lsb 24
#define reg_iop_sw_cfg_rw_bus_mask___byte3___width 8
#define reg_iop_sw_cfg_rw_bus_mask_offset 88

/* Register rw_bus_oe_mask, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___lsb 0
#define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___width 1
#define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___bit 0
#define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___lsb 1
#define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___width 1
#define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___bit 1
#define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___lsb 2
#define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___width 1
#define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___bit 2
#define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___lsb 3
#define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___width 1
#define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___bit 3
#define reg_iop_sw_cfg_rw_bus_oe_mask_offset 92

/* Register rw_gio_mask, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_gio_mask___val___lsb 0
#define reg_iop_sw_cfg_rw_gio_mask___val___width 32
#define reg_iop_sw_cfg_rw_gio_mask_offset 96

/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_gio_oe_mask___val___lsb 0
#define reg_iop_sw_cfg_rw_gio_oe_mask___val___width 32
#define reg_iop_sw_cfg_rw_gio_oe_mask_offset 100

/* Register rw_pinmapping, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_pinmapping___bus_byte0___lsb 0
#define reg_iop_sw_cfg_rw_pinmapping___bus_byte0___width 2
#define reg_iop_sw_cfg_rw_pinmapping___bus_byte1___lsb 2
#define reg_iop_sw_cfg_rw_pinmapping___bus_byte1___width 2
#define reg_iop_sw_cfg_rw_pinmapping___bus_byte2___lsb 4
#define reg_iop_sw_cfg_rw_pinmapping___bus_byte2___width 2
#define reg_iop_sw_cfg_rw_pinmapping___bus_byte3___lsb 6
#define reg_iop_sw_cfg_rw_pinmapping___bus_byte3___width 2
#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___lsb 8
#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___width 2
#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___lsb 10
#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___width 2
#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___lsb 12
#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___width 2
#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___lsb 14
#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___width 2
#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___lsb 16
#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___width 2
#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___lsb 18
#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___width 2
#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___lsb 20
#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___width 2
#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___lsb 22
#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___width 2
#define reg_iop_sw_cfg_rw_pinmapping_offset 104

/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo___lsb 0
#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo___width 2
#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi___lsb 2
#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi___width 2
#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo_oe___lsb 4
#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo_oe___width 2
#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi_oe___lsb 6
#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi_oe___width 2
#define reg_iop_sw_cfg_rw_bus_out_cfg_offset 108

/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___lsb 0
#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___width 3
#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___lsb 3
#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___width 1
#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___bit 3
#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___lsb 4
#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___width 3
#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___lsb 7
#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___width 1