📄 iop_sw_cpu_defs.h
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unsigned int mpu_6 : 1; unsigned int mpu_7 : 1; unsigned int mpu_8 : 1; unsigned int mpu_9 : 1; unsigned int mpu_10 : 1; unsigned int mpu_11 : 1; unsigned int mpu_12 : 1; unsigned int mpu_13 : 1; unsigned int mpu_14 : 1; unsigned int mpu_15 : 1; unsigned int spu_0 : 1; unsigned int spu_1 : 1; unsigned int spu_2 : 1; unsigned int spu_3 : 1; unsigned int spu_4 : 1; unsigned int spu_5 : 1; unsigned int spu_6 : 1; unsigned int spu_7 : 1; unsigned int spu_8 : 1; unsigned int spu_9 : 1; unsigned int spu_10 : 1; unsigned int spu_11 : 1; unsigned int spu_12 : 1; unsigned int spu_13 : 1; unsigned int spu_14 : 1; unsigned int spu_15 : 1;} reg_iop_sw_cpu_rw_ack_intr0;#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr0 80#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr0 80/* Register r_intr0, scope iop_sw_cpu, type r */typedef struct { unsigned int mpu_0 : 1; unsigned int mpu_1 : 1; unsigned int mpu_2 : 1; unsigned int mpu_3 : 1; unsigned int mpu_4 : 1; unsigned int mpu_5 : 1; unsigned int mpu_6 : 1; unsigned int mpu_7 : 1; unsigned int mpu_8 : 1; unsigned int mpu_9 : 1; unsigned int mpu_10 : 1; unsigned int mpu_11 : 1; unsigned int mpu_12 : 1; unsigned int mpu_13 : 1; unsigned int mpu_14 : 1; unsigned int mpu_15 : 1; unsigned int spu_0 : 1; unsigned int spu_1 : 1; unsigned int spu_2 : 1; unsigned int spu_3 : 1; unsigned int spu_4 : 1; unsigned int spu_5 : 1; unsigned int spu_6 : 1; unsigned int spu_7 : 1; unsigned int spu_8 : 1; unsigned int spu_9 : 1; unsigned int spu_10 : 1; unsigned int spu_11 : 1; unsigned int spu_12 : 1; unsigned int spu_13 : 1; unsigned int spu_14 : 1; unsigned int spu_15 : 1;} reg_iop_sw_cpu_r_intr0;#define REG_RD_ADDR_iop_sw_cpu_r_intr0 84/* Register r_masked_intr0, scope iop_sw_cpu, type r */typedef struct { unsigned int mpu_0 : 1; unsigned int mpu_1 : 1; unsigned int mpu_2 : 1; unsigned int mpu_3 : 1; unsigned int mpu_4 : 1; unsigned int mpu_5 : 1; unsigned int mpu_6 : 1; unsigned int mpu_7 : 1; unsigned int mpu_8 : 1; unsigned int mpu_9 : 1; unsigned int mpu_10 : 1; unsigned int mpu_11 : 1; unsigned int mpu_12 : 1; unsigned int mpu_13 : 1; unsigned int mpu_14 : 1; unsigned int mpu_15 : 1; unsigned int spu_0 : 1; unsigned int spu_1 : 1; unsigned int spu_2 : 1; unsigned int spu_3 : 1; unsigned int spu_4 : 1; unsigned int spu_5 : 1; unsigned int spu_6 : 1; unsigned int spu_7 : 1; unsigned int spu_8 : 1; unsigned int spu_9 : 1; unsigned int spu_10 : 1; unsigned int spu_11 : 1; unsigned int spu_12 : 1; unsigned int spu_13 : 1; unsigned int spu_14 : 1; unsigned int spu_15 : 1;} reg_iop_sw_cpu_r_masked_intr0;#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr0 88/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */typedef struct { unsigned int mpu_16 : 1; unsigned int mpu_17 : 1; unsigned int mpu_18 : 1; unsigned int mpu_19 : 1; unsigned int mpu_20 : 1; unsigned int mpu_21 : 1; unsigned int mpu_22 : 1; unsigned int mpu_23 : 1; unsigned int mpu_24 : 1; unsigned int mpu_25 : 1; unsigned int mpu_26 : 1; unsigned int mpu_27 : 1; unsigned int mpu_28 : 1; unsigned int mpu_29 : 1; unsigned int mpu_30 : 1; unsigned int mpu_31 : 1; unsigned int dmc_in : 1; unsigned int dmc_out : 1; unsigned int fifo_in : 1; unsigned int fifo_out : 1; unsigned int fifo_in_extra : 1; unsigned int fifo_out_extra : 1; unsigned int trigger_grp0 : 1; unsigned int trigger_grp1 : 1; unsigned int trigger_grp2 : 1; unsigned int trigger_grp3 : 1; unsigned int trigger_grp4 : 1; unsigned int trigger_grp5 : 1; unsigned int trigger_grp6 : 1; unsigned int trigger_grp7 : 1; unsigned int timer_grp0 : 1; unsigned int timer_grp1 : 1;} reg_iop_sw_cpu_rw_intr1_mask;#define REG_RD_ADDR_iop_sw_cpu_rw_intr1_mask 92#define REG_WR_ADDR_iop_sw_cpu_rw_intr1_mask 92/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */typedef struct { unsigned int mpu_16 : 1; unsigned int mpu_17 : 1; unsigned int mpu_18 : 1; unsigned int mpu_19 : 1; unsigned int mpu_20 : 1; unsigned int mpu_21 : 1; unsigned int mpu_22 : 1; unsigned int mpu_23 : 1; unsigned int mpu_24 : 1; unsigned int mpu_25 : 1; unsigned int mpu_26 : 1; unsigned int mpu_27 : 1; unsigned int mpu_28 : 1; unsigned int mpu_29 : 1; unsigned int mpu_30 : 1; unsigned int mpu_31 : 1; unsigned int dummy1 : 16;} reg_iop_sw_cpu_rw_ack_intr1;#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr1 96#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr1 96/* Register r_intr1, scope iop_sw_cpu, type r */typedef struct { unsigned int mpu_16 : 1; unsigned int mpu_17 : 1; unsigned int mpu_18 : 1; unsigned int mpu_19 : 1; unsigned int mpu_20 : 1; unsigned int mpu_21 : 1; unsigned int mpu_22 : 1; unsigned int mpu_23 : 1; unsigned int mpu_24 : 1; unsigned int mpu_25 : 1; unsigned int mpu_26 : 1; unsigned int mpu_27 : 1; unsigned int mpu_28 : 1; unsigned int mpu_29 : 1; unsigned int mpu_30 : 1; unsigned int mpu_31 : 1; unsigned int dmc_in : 1; unsigned int dmc_out : 1; unsigned int fifo_in : 1; unsigned int fifo_out : 1; unsigned int fifo_in_extra : 1; unsigned int fifo_out_extra : 1; unsigned int trigger_grp0 : 1; unsigned int trigger_grp1 : 1; unsigned int trigger_grp2 : 1; unsigned int trigger_grp3 : 1; unsigned int trigger_grp4 : 1; unsigned int trigger_grp5 : 1; unsigned int trigger_grp6 : 1; unsigned int trigger_grp7 : 1; unsigned int timer_grp0 : 1; unsigned int timer_grp1 : 1;} reg_iop_sw_cpu_r_intr1;#define REG_RD_ADDR_iop_sw_cpu_r_intr1 100/* Register r_masked_intr1, scope iop_sw_cpu, type r */typedef struct { unsigned int mpu_16 : 1; unsigned int mpu_17 : 1; unsigned int mpu_18 : 1; unsigned int mpu_19 : 1; unsigned int mpu_20 : 1; unsigned int mpu_21 : 1; unsigned int mpu_22 : 1; unsigned int mpu_23 : 1; unsigned int mpu_24 : 1; unsigned int mpu_25 : 1; unsigned int mpu_26 : 1; unsigned int mpu_27 : 1; unsigned int mpu_28 : 1; unsigned int mpu_29 : 1; unsigned int mpu_30 : 1; unsigned int mpu_31 : 1; unsigned int dmc_in : 1; unsigned int dmc_out : 1; unsigned int fifo_in : 1; unsigned int fifo_out : 1; unsigned int fifo_in_extra : 1; unsigned int fifo_out_extra : 1; unsigned int trigger_grp0 : 1; unsigned int trigger_grp1 : 1; unsigned int trigger_grp2 : 1; unsigned int trigger_grp3 : 1; unsigned int trigger_grp4 : 1; unsigned int trigger_grp5 : 1; unsigned int trigger_grp6 : 1; unsigned int trigger_grp7 : 1; unsigned int timer_grp0 : 1; unsigned int timer_grp1 : 1;} reg_iop_sw_cpu_r_masked_intr1;#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr1 104/* Constants */enum { regk_iop_sw_cpu_copy = 0x00000000, regk_iop_sw_cpu_no = 0x00000000, regk_iop_sw_cpu_rd = 0x00000002, regk_iop_sw_cpu_reg_copy = 0x00000001, regk_iop_sw_cpu_rw_bus_clr_mask_default = 0x00000000, regk_iop_sw_cpu_rw_bus_oe_clr_mask_default = 0x00000000, regk_iop_sw_cpu_rw_bus_oe_set_mask_default = 0x00000000, regk_iop_sw_cpu_rw_bus_set_mask_default = 0x00000000, regk_iop_sw_cpu_rw_gio_clr_mask_default = 0x00000000, regk_iop_sw_cpu_rw_gio_oe_clr_mask_default = 0x00000000, regk_iop_sw_cpu_rw_gio_oe_set_mask_default = 0x00000000, regk_iop_sw_cpu_rw_gio_set_mask_default = 0x00000000, regk_iop_sw_cpu_rw_intr0_mask_default = 0x00000000, regk_iop_sw_cpu_rw_intr1_mask_default = 0x00000000, regk_iop_sw_cpu_wr = 0x00000003, regk_iop_sw_cpu_yes = 0x00000001};#endif /* __iop_sw_cpu_defs_h */⌨️ 快捷键说明
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