i2o.h

Axis 221 camera embedded programing interface

	struct i2o_controller *iop;	/* Controlling IOP */
	struct list_head list;	/* node in IOP devices list */

	struct device device;

	struct semaphore lock;	/* device lock */
};

/*
 *	Event structure provided to the event handling function
 */
struct i2o_event {
	struct work_struct work;
	struct i2o_device *i2o_dev;	/* I2O device pointer from which the
					   event reply was initiated */
	u16 size;		/* Size of data in 32-bit words */
	u32 tcntxt;		/* Transaction context used at
				   registration */
	u32 event_indicator;	/* Event indicator from reply */
	u32 data[0];		/* Event data from reply */
};

/*
 *	I2O classes which could be handled by the OSM
 */
struct i2o_class_id {
	u16 class_id:12;
};

/*
 *	I2O driver structure for OSMs
 */
struct i2o_driver {
	char *name;		/* OSM name */
	int context;		/* Low 8 bits of the transaction info */
	struct i2o_class_id *classes;	/* I2O classes that this OSM handles */

	/* Message reply handler */
	int (*reply) (struct i2o_controller *, u32, struct i2o_message *);

	/* Event handler */
	work_func_t event;

	struct workqueue_struct *event_queue;	/* Event queue */

	struct device_driver driver;

	/* notification of changes */
	void (*notify_controller_add) (struct i2o_controller *);
	void (*notify_controller_remove) (struct i2o_controller *);
	void (*notify_device_add) (struct i2o_device *);
	void (*notify_device_remove) (struct i2o_device *);

	struct semaphore lock;
};

/*
 *	Contains DMA mapped address information
 */
struct i2o_dma {
	void *virt;
	dma_addr_t phys;
	size_t len;
};

/*
 *	Contains slab cache and mempool information
 */
struct i2o_pool {
	char *name;
	struct kmem_cache *slab;
	mempool_t *mempool;
};

/*
 *	Contains IO mapped address information
 */
struct i2o_io {
	void __iomem *virt;
	unsigned long phys;
	unsigned long len;
};

/*
 *	Context queue entry, used for 32-bit context on 64-bit systems
 */
struct i2o_context_list_element {
	struct list_head list;
	u32 context;
	void *ptr;
	unsigned long timestamp;
};

/*
 * Each I2O controller has one of these objects
 */
struct i2o_controller {
	char name[16];
	int unit;
	int type;

	struct pci_dev *pdev;	/* PCI device */

	unsigned int promise:1;	/* Promise controller */
	unsigned int adaptec:1;	/* DPT / Adaptec controller */
	unsigned int raptor:1;	/* split bar */
	unsigned int no_quiesce:1;	/* dont quiesce before reset */
	unsigned int short_req:1;	/* use small block sizes */
	unsigned int limit_sectors:1;	/* limit number of sectors / request */
	unsigned int pae_support:1;	/* controller has 64-bit SGL support */

	struct list_head devices;	/* list of I2O devices */
	struct list_head list;	/* Controller list */

	void __iomem *in_port;	/* Inbout port address */
	void __iomem *out_port;	/* Outbound port address */
	void __iomem *irq_status;	/* Interrupt status register address */
	void __iomem *irq_mask;	/* Interrupt mask register address */

	struct i2o_dma status;	/* IOP status block */

	struct i2o_dma hrt;	/* HW Resource Table */
	i2o_lct *lct;		/* Logical Config Table */
	struct i2o_dma dlct;	/* Temp LCT */
	struct semaphore lct_lock;	/* Lock for LCT updates */
	struct i2o_dma status_block;	/* IOP status block */

	struct i2o_io base;	/* controller messaging unit */
	struct i2o_io in_queue;	/* inbound message queue Host->IOP */
	struct i2o_dma out_queue;	/* outbound message queue IOP->Host */

	struct i2o_pool in_msg;	/* mempool for inbound messages */

	unsigned int battery:1;	/* Has a battery backup */
	unsigned int io_alloc:1;	/* An I/O resource was allocated */
	unsigned int mem_alloc:1;	/* A memory resource was allocated */

	struct resource io_resource;	/* I/O resource allocated to the IOP */
	struct resource mem_resource;	/* Mem resource allocated to the IOP */

	struct device device;
	struct i2o_device *exec;	/* Executive */
#if BITS_PER_LONG == 64
	spinlock_t context_list_lock;	/* lock for context_list */
	atomic_t context_list_counter;	/* needed for unique contexts */
	struct list_head context_list;	/* list of context id's
					   and pointers */
#endif
	spinlock_t lock;	/* lock for controller
				   configuration */

	void *driver_data[I2O_MAX_DRIVERS];	/* storage for drivers */
};

/*
 * I2O System table entry
 *
 * The system table contains information about all the IOPs in the
 * system.  It is sent to all IOPs so that they can create peer2peer
 * connections between them.
 */
struct i2o_sys_tbl_entry {
	u16 org_id;
	u16 reserved1;
	u32 iop_id:12;
	u32 reserved2:20;
	u16 seg_num:12;
	u16 i2o_version:4;
	u8 iop_state;
	u8 msg_type;
	u16 frame_size;
	u16 reserved3;
	u32 last_changed;
	u32 iop_capabilities;
	u32 inbound_low;
	u32 inbound_high;
};

struct i2o_sys_tbl {
	u8 num_entries;
	u8 version;
	u16 reserved1;
	u32 change_ind;
	u32 reserved2;
	u32 reserved3;
	struct i2o_sys_tbl_entry iops[0];
};

extern struct list_head i2o_controllers;

/* Message functions */
static inline struct i2o_message *i2o_msg_get(struct i2o_controller *);
extern struct i2o_message *i2o_msg_get_wait(struct i2o_controller *, int);
static inline void i2o_msg_post(struct i2o_controller *, struct i2o_message *);
static inline int i2o_msg_post_wait(struct i2o_controller *,
				    struct i2o_message *, unsigned long);
extern int i2o_msg_post_wait_mem(struct i2o_controller *, struct i2o_message *,
				 unsigned long, struct i2o_dma *);
static inline void i2o_flush_reply(struct i2o_controller *, u32);

/* IOP functions */
extern int i2o_status_get(struct i2o_controller *);

extern int i2o_event_register(struct i2o_device *, struct i2o_driver *, int,
			      u32);
extern struct i2o_device *i2o_iop_find_device(struct i2o_controller *, u16);
extern struct i2o_controller *i2o_find_iop(int);

/* Functions needed for handling 64-bit pointers in 32-bit context */
#if BITS_PER_LONG == 64
extern u32 i2o_cntxt_list_add(struct i2o_controller *, void *);
extern void *i2o_cntxt_list_get(struct i2o_controller *, u32);
extern u32 i2o_cntxt_list_remove(struct i2o_controller *, void *);
extern u32 i2o_cntxt_list_get_ptr(struct i2o_controller *, void *);

static inline u32 i2o_ptr_low(void *ptr)
{
	return (u32) (u64) ptr;
};

static inline u32 i2o_ptr_high(void *ptr)
{
	return (u32) ((u64) ptr >> 32);
};

static inline u32 i2o_dma_low(dma_addr_t dma_addr)
{
	return (u32) (u64) dma_addr;
};

static inline u32 i2o_dma_high(dma_addr_t dma_addr)
{
	return (u32) ((u64) dma_addr >> 32);
};
#else
static inline u32 i2o_cntxt_list_add(struct i2o_controller *c, void *ptr)
{
	return (u32) ptr;
};

static inline void *i2o_cntxt_list_get(struct i2o_controller *c, u32 context)
{
	return (void *)context;
};

static inline u32 i2o_cntxt_list_remove(struct i2o_controller *c, void *ptr)
{
	return (u32) ptr;
};

static inline u32 i2o_cntxt_list_get_ptr(struct i2o_controller *c, void *ptr)
{
	return (u32) ptr;
};

static inline u32 i2o_ptr_low(void *ptr)
{
	return (u32) ptr;
};

static inline u32 i2o_ptr_high(void *ptr)
{
	return 0;
};

static inline u32 i2o_dma_low(dma_addr_t dma_addr)
{
	return (u32) dma_addr;
};

static inline u32 i2o_dma_high(dma_addr_t dma_addr)
{
	return 0;
};
#endif

/**
 *	i2o_sg_tablesize - Calculate the maximum number of elements in a SGL
 *	@c: I2O controller for which the calculation should be done
 *	@body_size: maximum body size used for message in 32-bit words.
 *
 *	Return the maximum number of SG elements in a SG list.
 */
static inline u16 i2o_sg_tablesize(struct i2o_controller *c, u16 body_size)
{
	i2o_status_block *sb = c->status_block.virt;
	u16 sg_count =
	    (sb->inbound_frame_size - sizeof(struct i2o_message) / 4) -
	    body_size;

	if (c->pae_support) {
		/*
		 * for 64-bit a SG attribute element must be added and each
		 * SG element needs 12 bytes instead of 8.
		 */
		sg_count -= 2;
		sg_count /= 3;
	} else
		sg_count /= 2;

	if (c->short_req && (sg_count > 8))
		sg_count = 8;

	return sg_count;
};

/**
 *	i2o_dma_map_single - Map pointer to controller and fill in I2O message.
 *	@c: I2O controller
 *	@ptr: pointer to the data which should be mapped
 *	@size: size of data in bytes
 *	@direction: DMA_TO_DEVICE / DMA_FROM_DEVICE
 *	@sg_ptr: pointer to the SG list inside the I2O message
 *
 *	This function does all necessary DMA handling and also writes the I2O
 *	SGL elements into the I2O message. For details on DMA handling see also
 *	dma_map_single(). The pointer sg_ptr will only be set to the end of the
 *	SG list if the allocation was successful.
 *
 *	Returns DMA address which must be checked for failures using
 *	dma_mapping_error().
 */
static inline dma_addr_t i2o_dma_map_single(struct i2o_controller *c, void *ptr,
					    size_t size,
					    enum dma_data_direction direction,
					    u32 ** sg_ptr)
{
	u32 sg_flags;
	u32 *mptr = *sg_ptr;
	dma_addr_t dma_addr;

	switch (direction) {
	case DMA_TO_DEVICE:
		sg_flags = 0xd4000000;
		break;
	case DMA_FROM_DEVICE:
		sg_flags = 0xd0000000;
		break;
	default:
		return 0;
	}

	dma_addr = dma_map_single(&c->pdev->dev, ptr, size, direction);
	if (!dma_mapping_error(dma_addr)) {
#ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
		if ((sizeof(dma_addr_t) > 4) && c->pae_support) {
			*mptr++ = cpu_to_le32(0x7C020002);
			*mptr++ = cpu_to_le32(PAGE_SIZE);
		}
#endif

		*mptr++ = cpu_to_le32(sg_flags | size);
		*mptr++ = cpu_to_le32(i2o_dma_low(dma_addr));
#ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
		if ((sizeof(dma_addr_t) > 4) && c->pae_support)
			*mptr++ = cpu_to_le32(i2o_dma_high(dma_addr));
#endif
		*sg_ptr = mptr;
	}
	return dma_addr;
};

/**
 *	i2o_dma_map_sg - Map a SG List to controller and fill in I2O message.
 *	@c: I2O controller
 *	@sg: SG list to be mapped
 *	@sg_count: number of elements in the SG list
 *	@direction: DMA_TO_DEVICE / DMA_FROM_DEVICE
 *	@sg_ptr: pointer to the SG list inside the I2O message
 *
 *	This function does all necessary DMA handling and also writes the I2O
 *	SGL elements into the I2O message. For details on DMA handling see also
 *	dma_map_sg(). The pointer sg_ptr will only be set to the end of the SG
 *	list if the allocation was successful.
 *
 *	Returns 0 on failure or 1 on success.
 */
static inline int i2o_dma_map_sg(struct i2o_controller *c,
				 struct scatterlist *sg, int sg_count,
				 enum dma_data_direction direction,
				 u32 ** sg_ptr)
{
	u32 sg_flags;
	u32 *mptr = *sg_ptr;

	switch (direction) {
	case DMA_TO_DEVICE:
		sg_flags = 0x14000000;
		break;
	case DMA_FROM_DEVICE:
		sg_flags = 0x10000000;
		break;
	default:
		return 0;
	}

	sg_count = dma_map_sg(&c->pdev->dev, sg, sg_count, direction);
	if (!sg_count)
		return 0;

#ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
	if ((sizeof(dma_addr_t) > 4) && c->pae_support) {
		*mptr++ = cpu_to_le32(0x7C020002);
		*mptr++ = cpu_to_le32(PAGE_SIZE);
	}
#endif

	while (sg_count-- > 0) {
		if (!sg_count)
			sg_flags |= 0xC0000000;
		*mptr++ = cpu_to_le32(sg_flags | sg_dma_len(sg));
		*mptr++ = cpu_to_le32(i2o_dma_low(sg_dma_address(sg)));
#ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
		if ((sizeof(dma_addr_t) > 4) && c->pae_support)
			*mptr++ = cpu_to_le32(i2o_dma_high(sg_dma_address(sg)));
#endif
		sg++;
	}
	*sg_ptr = mptr;

	return 1;
};