📄 mv643xx.h
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#define MV64340_DMA_BASE_ADDR_REG6 0xa30#define MV64340_DMA_BASE_ADDR_REG7 0xa38 /* IDMA Address Decoding Size Address Register */ #define MV64340_DMA_SIZE_REG0 0xa04#define MV64340_DMA_SIZE_REG1 0xa0c#define MV64340_DMA_SIZE_REG2 0xa14#define MV64340_DMA_SIZE_REG3 0xa1c#define MV64340_DMA_SIZE_REG4 0xa24#define MV64340_DMA_SIZE_REG5 0xa2c#define MV64340_DMA_SIZE_REG6 0xa34#define MV64340_DMA_SIZE_REG7 0xa3C /* IDMA Address Decoding High Address Remap and Access Protection Registers */ #define MV64340_DMA_HIGH_ADDR_REMAP_REG0 0xa60#define MV64340_DMA_HIGH_ADDR_REMAP_REG1 0xa64#define MV64340_DMA_HIGH_ADDR_REMAP_REG2 0xa68#define MV64340_DMA_HIGH_ADDR_REMAP_REG3 0xa6C#define MV64340_DMA_BASE_ADDR_ENABLE_REG 0xa80#define MV64340_DMA_CHANNEL0_ACCESS_PROTECTION_REG 0xa70#define MV64340_DMA_CHANNEL1_ACCESS_PROTECTION_REG 0xa74#define MV64340_DMA_CHANNEL2_ACCESS_PROTECTION_REG 0xa78#define MV64340_DMA_CHANNEL3_ACCESS_PROTECTION_REG 0xa7c#define MV64340_DMA_ARBITER_CONTROL 0x860#define MV64340_DMA_CROSS_BAR_TIMEOUT 0x8d0 /* IDMA Headers Retarget Registers */#define MV64340_DMA_HEADERS_RETARGET_CONTROL 0xa84#define MV64340_DMA_HEADERS_RETARGET_BASE 0xa88 /* IDMA Interrupt Register */#define MV64340_DMA_INTERRUPT_CAUSE_REG 0x8c0#define MV64340_DMA_INTERRUPT_CAUSE_MASK 0x8c4#define MV64340_DMA_ERROR_ADDR 0x8c8#define MV64340_DMA_ERROR_SELECT 0x8cc /* IDMA Debug Register ( for internal use ) */#define MV64340_DMA_DEBUG_LOW 0x8e0#define MV64340_DMA_DEBUG_HIGH 0x8e4#define MV64340_DMA_SPARE 0xA8C/****************************************//* Timer_Counter *//****************************************/#define MV64340_TIMER_COUNTER0 0x850#define MV64340_TIMER_COUNTER1 0x854#define MV64340_TIMER_COUNTER2 0x858#define MV64340_TIMER_COUNTER3 0x85C#define MV64340_TIMER_COUNTER_0_3_CONTROL 0x864#define MV64340_TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868#define MV64340_TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c/****************************************//* Watchdog registers *//****************************************/#define MV64340_WATCHDOG_CONFIG_REG 0xb410#define MV64340_WATCHDOG_VALUE_REG 0xb414/****************************************//* I2C Registers *//****************************************/#define MV64XXX_I2C_CTLR_NAME "mv64xxx_i2c"#define MV64XXX_I2C_OFFSET 0xc000#define MV64XXX_I2C_REG_BLOCK_SIZE 0x0020/****************************************//* GPP Interface Registers *//****************************************/#define MV64340_GPP_IO_CONTROL 0xf100#define MV64340_GPP_LEVEL_CONTROL 0xf110#define MV64340_GPP_VALUE 0xf104#define MV64340_GPP_INTERRUPT_CAUSE 0xf108#define MV64340_GPP_INTERRUPT_MASK0 0xf10c#define MV64340_GPP_INTERRUPT_MASK1 0xf114#define MV64340_GPP_VALUE_SET 0xf118#define MV64340_GPP_VALUE_CLEAR 0xf11c/****************************************//* Interrupt Controller Registers *//****************************************//****************************************//* Interrupts *//****************************************/#define MV64340_MAIN_INTERRUPT_CAUSE_LOW 0x004#define MV64340_MAIN_INTERRUPT_CAUSE_HIGH 0x00c#define MV64340_CPU_INTERRUPT0_MASK_LOW 0x014#define MV64340_CPU_INTERRUPT0_MASK_HIGH 0x01c#define MV64340_CPU_INTERRUPT0_SELECT_CAUSE 0x024#define MV64340_CPU_INTERRUPT1_MASK_LOW 0x034#define MV64340_CPU_INTERRUPT1_MASK_HIGH 0x03c#define MV64340_CPU_INTERRUPT1_SELECT_CAUSE 0x044#define MV64340_INTERRUPT0_MASK_0_LOW 0x054#define MV64340_INTERRUPT0_MASK_0_HIGH 0x05c#define MV64340_INTERRUPT0_SELECT_CAUSE 0x064#define MV64340_INTERRUPT1_MASK_0_LOW 0x074#define MV64340_INTERRUPT1_MASK_0_HIGH 0x07c#define MV64340_INTERRUPT1_SELECT_CAUSE 0x084/****************************************//* MPP Interface Registers *//****************************************/#define MV64340_MPP_CONTROL0 0xf000#define MV64340_MPP_CONTROL1 0xf004#define MV64340_MPP_CONTROL2 0xf008#define MV64340_MPP_CONTROL3 0xf00c/****************************************//* Serial Initialization registers *//****************************************/#define MV64340_SERIAL_INIT_LAST_DATA 0xf324#define MV64340_SERIAL_INIT_CONTROL 0xf328#define MV64340_SERIAL_INIT_STATUS 0xf32cextern void mv64340_irq_init(unsigned int base);/* MPSC Platform Device, Driver Data (Shared register regions) */#define MPSC_SHARED_NAME "mpsc_shared"#define MPSC_ROUTING_BASE_ORDER 0#define MPSC_SDMA_INTR_BASE_ORDER 1#define MPSC_ROUTING_REG_BLOCK_SIZE 0x000c#define MPSC_SDMA_INTR_REG_BLOCK_SIZE 0x0084struct mpsc_shared_pdata { u32 mrr_val; u32 rcrr_val; u32 tcrr_val; u32 intr_cause_val; u32 intr_mask_val;};/* MPSC Platform Device, Driver Data */#define MPSC_CTLR_NAME "mpsc"#define MPSC_BASE_ORDER 0#define MPSC_SDMA_BASE_ORDER 1#define MPSC_BRG_BASE_ORDER 2#define MPSC_REG_BLOCK_SIZE 0x0038#define MPSC_SDMA_REG_BLOCK_SIZE 0x0c18#define MPSC_BRG_REG_BLOCK_SIZE 0x0008struct mpsc_pdata { u8 mirror_regs; u8 cache_mgmt; u8 max_idle; int default_baud; int default_bits; int default_parity; int default_flow; u32 chr_1_val; u32 chr_2_val; u32 chr_10_val; u32 mpcr_val; u32 bcr_val; u8 brg_can_tune; u8 brg_clk_src; u32 brg_clk_freq;};/* i2c Platform Device, Driver Data */struct mv64xxx_i2c_pdata { u32 freq_m; u32 freq_n; u32 timeout; /* In milliseconds */ u32 retries;};/* These macros describe Ethernet Port configuration reg (Px_cR) bits */#define MV643XX_ETH_UNICAST_NORMAL_MODE 0#define MV643XX_ETH_UNICAST_PROMISCUOUS_MODE (1<<0)#define MV643XX_ETH_DEFAULT_RX_QUEUE_0 0#define MV643XX_ETH_DEFAULT_RX_QUEUE_1 (1<<1)#define MV643XX_ETH_DEFAULT_RX_QUEUE_2 (1<<2)#define MV643XX_ETH_DEFAULT_RX_QUEUE_3 ((1<<2) | (1<<1))#define MV643XX_ETH_DEFAULT_RX_QUEUE_4 (1<<3)#define MV643XX_ETH_DEFAULT_RX_QUEUE_5 ((1<<3) | (1<<1))#define MV643XX_ETH_DEFAULT_RX_QUEUE_6 ((1<<3) | (1<<2))#define MV643XX_ETH_DEFAULT_RX_QUEUE_7 ((1<<3) | (1<<2) | (1<<1))#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_0 0#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_1 (1<<4)#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_2 (1<<5)#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_3 ((1<<5) | (1<<4))#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_4 (1<<6)#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_5 ((1<<6) | (1<<4))#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_6 ((1<<6) | (1<<5))#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_7 ((1<<6) | (1<<5) | (1<<4))#define MV643XX_ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0#define MV643XX_ETH_REJECT_BC_IF_NOT_IP_OR_ARP (1<<7)#define MV643XX_ETH_RECEIVE_BC_IF_IP 0#define MV643XX_ETH_REJECT_BC_IF_IP (1<<8)#define MV643XX_ETH_RECEIVE_BC_IF_ARP 0#define MV643XX_ETH_REJECT_BC_IF_ARP (1<<9)#define MV643XX_ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY (1<<12)#define MV643XX_ETH_CAPTURE_TCP_FRAMES_DIS 0#define MV643XX_ETH_CAPTURE_TCP_FRAMES_EN (1<<14)#define MV643XX_ETH_CAPTURE_UDP_FRAMES_DIS 0#define MV643XX_ETH_CAPTURE_UDP_FRAMES_EN (1<<15)#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_0 0#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_1 (1<<16)#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_2 (1<<17)#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_3 ((1<<17) | (1<<16))#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_4 (1<<18)#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_5 ((1<<18) | (1<<16))#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_6 ((1<<18) | (1<<17))#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_7 ((1<<18) | (1<<17) | (1<<16))#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_0 0#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_1 (1<<19)#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_2 (1<<20)#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_3 ((1<<20) | (1<<19))#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_4 (1<⌨️ 快捷键说明
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