bell.v

来自「数字钟 可实现正常计数校准 还有方电台报时功能 四低一高 闹钟功能」· Verilog 代码 · 共 27 行

module Bell(Alarm_clock,Set_Hr,Set_Min,Hour,Minute,Second,SetHrkey,
			SetMinkey,_1kHz,_500Hz,_1Hz,CtrlBell);
	output Alarm_clock;
	output [7:0]Set_Hr,Set_Min;
	wire[7:0]Set_Hr,Set_Min;
	wire Alarm_clock;
	input _1kHz,_500Hz,_1Hz;
	input SetHrkey,SetMinkey;
	input CtrlBell;
	input [7:0]Hour,Minute,Second;
	supply1 Vdd;
	wire HrH_EQU,HrL_EQU,MinH_EQU,MinL_EQU;
	wire Time_EQU;

	counter60 SU1(Set_Min,Vdd,SetMinkey,_1Hz);
	counter24 SU2(Set_Hr[7:4],Set_Hr[3:0],Vdd,SetHrkey,_1Hz);
	cmp	SU3 (HrH_EQU,Set_Hr[7:4],Hour[7:4]);
	cmp SU4 (HrL_EQU,Set_Hr[3:0],Hour[3:0]);
	cmp SU5 (MinH_EQU,Set_Min[7:4],Minute[7:4]);
	cmp SU6 (MinL_EQU,Set_Min[3:0],Minute[3:0]);
	
	assign Time_EQU=(HrH_EQU&&HrL_EQU&&MinH_EQU&&MinL_EQU);
	assign Alarm_clock=CtrlBell?(Time_EQU&&(((Second[0]==1'b1)&&_500Hz)||((Second[0]==1'b0)&&_1kHz))):1'b0;
	
endmodule