top_clock.v

来自「数字钟 可实现正常计数校准 还有方电台报时功能 四低一高 闹钟功能」· Verilog 代码 · 共 20 行

module top_clock (Hour,Minute,Second,CP,nCR,Adj_Min,Adj_Hour);
	input  CP,nCR,Adj_Min,Adj_Hour;
	output[7:0] Hour,Minute,Second;
	wire[7:0] Hour,Minute,Second;
	supply1 Vdd;
	wire Min_CP,Hour_CP;

	counter60 UT1(Second,nCR,Vdd,CP);
	counter60 UT2(Minute,nCR,Vdd,~Min_CP);
	counter24 UT3(Hour[7:4],Hour[3:0],nCR,Vdd,~Hour_CP);


	assign Min_CP=Adj_Min?CP:(Second==8'h59);
		assign Hour_CP=Adj_Hour?CP:((Minute==8'h59)&&(Second==8'h59));
endmodule