radio.v

来自「数字钟 可实现正常计数校准 还有方电台报时功能 四低一高 闹钟功能」· Verilog 代码 · 共 23 行

module Radio (ALARM_Radio,Minute,Second,_1kHz,_500Hz);
	input _1kHz,_500Hz;
	input  [7:0]Minute,Second;
	output ALARM_Radio;
	reg ALARM_Radio;
	always@(Minute or Second)
		begin
		 if(Minute==8'h59)
			begin
			case(Second)
				8'h51,
				8'h53,
				8'h55,
				8'h57:ALARM_Radio=_500Hz;
				8'h59:ALARM_Radio=_1kHz;
				default:ALARM_Radio=1'b0;
			endcase
			end
		else ALARM_Radio=1'b0;
	end
endmodule