untitled2.v

来自「数字钟 可实现正常计数校准 还有方电台报时功能 四低一高 闹钟功能」· Verilog 代码 · 共 23 行

module top_clock (Hour,miute,Second,CP,nCR,EN,Adj_Min,Adj_Hour)
	input  CP,nCR,EN,Adj_Min,Adj_Hour;
	output[7:0] Hour,Minute,Second;
	wire[7:0] Hour,Minute,Second;
	supply1 Vdd;
	wire MinL_EN,MinH_EN,Hour_EN;

	counter10 U1(Second[3:0],nCR,EN,CP);
	counter6 U2(Second[7:4],nCR,(Second[3:0]==4'h9),CP);
	assign MinL_EN=Adj_Min?VDD:(Second==8'h59);
	assign MinH_EN=(Adj_Min&&(MInute[3:0]==4'h9))||(Minute[3:0]==4'h9)&&(Second==8'h59);

	counter10 U3(Minute[3:0],nCR,MinL_EN,CP);
	counter6 U4(Minute[7:4],nCR,MinH_EN,CP);

	assign Hour_EN=Adj_Hour?VDD:(Minute==8'h59)&&(Second==8'h59);
	counter24 U5(Hour[7:4],Hour[3:0],nCR,Hour_EN,CP);
endmodule