📄 baoshi.rpt
字号:
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: g:\workhard\baoshi.rpt
baoshi
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - A 03 OR2 s ! 4 0 0 1 ~27~1
- 1 - C 11 OR2 s ! 4 0 0 1 ~27~2
- 3 - B 09 AND2 s 3 1 0 1 ~97~1
- 3 - B 03 AND2 s ! 1 1 0 1 ~116~1
- 1 - B 09 OR2 s ! 3 1 0 3 ~116~2
- 7 - B 09 OR2 s 3 1 0 1 ~221~1
- 6 - B 09 AND2 2 1 0 1 :240
- 8 - B 03 OR2 s ! 4 0 0 1 ~364~1
- 5 - B 03 AND2 s ! 3 1 0 3 ~364~2
- 4 - B 02 AND2 1 1 0 1 :382
- 5 - B 02 OR2 s 2 2 0 1 ~407~1
- 2 - B 07 AND2 2 0 0 4 :444
- 3 - B 02 OR2 s 2 2 0 1 ~469~1
- 7 - B 03 OR2 s ! 4 0 0 1 ~488~1
- 6 - B 03 AND2 s ! 3 1 0 3 ~488~2
- 6 - B 02 OR2 4 0 0 1 :504
- 2 - B 02 OR2 s 3 1 0 1 ~593~1
- 4 - B 03 OR2 s ! 4 0 0 2 ~612~1
- 1 - B 10 AND2 s ! 0 2 0 2 ~612~2
- 2 - B 11 AND2 2 1 0 1 :687
- 3 - B 11 OR2 s 2 2 0 1 ~717~1
- 2 - B 03 AND2 s ! 3 0 0 4 ~736~1
- 1 - B 03 OR2 s ! 3 1 0 5 ~736~2
- 4 - B 11 OR2 2 1 0 1 :747
- 5 - B 11 AND2 s 2 2 0 1 ~779~1
- 2 - B 08 AND2 s 0 2 0 1 ~792~1
- 2 - B 09 OR2 s 0 3 0 1 ~792~2
- 1 - B 08 AND2 s 0 3 0 1 ~792~3
- 1 - B 11 AND2 s 4 0 0 1 ~793~1
- 4 - B 09 OR2 s 2 2 0 1 ~793~2
- 8 - B 09 OR2 s 1 3 0 1 ~793~3
- 5 - B 09 OR2 s 2 2 0 1 ~793~4
- 7 - B 02 OR2 s 1 3 0 1 ~793~5
- 8 - B 02 OR2 s 1 3 0 1 ~793~6
- 1 - B 02 OR2 s 1 3 0 1 ~793~7
- 6 - B 11 OR2 s 1 3 0 1 ~793~8
- 7 - B 11 OR2 0 4 0 1 :793
- 8 - B 11 OR2 0 3 1 1 :799
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: g:\workhard\baoshi.rpt
baoshi
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 4/ 96( 4%) 0/ 48( 0%) 0/ 48( 0%) 4/16( 25%) 0/16( 0%) 0/16( 0%)
B: 13/ 96( 13%) 13/ 48( 27%) 0/ 48( 0%) 8/16( 50%) 1/16( 6%) 0/16( 0%)
C: 4/ 96( 4%) 0/ 48( 0%) 0/ 48( 0%) 4/16( 25%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: g:\workhard\baoshi.rpt
baoshi
** EQUATIONS **
hour0 : INPUT;
hour1 : INPUT;
hour2 : INPUT;
hour3 : INPUT;
hour4 : INPUT;
hour5 : INPUT;
hour6 : INPUT;
hour7 : INPUT;
hz1k : INPUT;
minute0 : INPUT;
minute1 : INPUT;
minute2 : INPUT;
minute3 : INPUT;
minute4 : INPUT;
minute5 : INPUT;
minute6 : INPUT;
minute7 : INPUT;
second0 : INPUT;
second1 : INPUT;
second2 : INPUT;
second3 : INPUT;
second4 : INPUT;
second5 : INPUT;
second6 : INPUT;
second7 : INPUT;
-- Node name is 'alarm'
-- Equation name is 'alarm', type is output
alarm = _LC8_B11;
-- Node name is '~27~1'
-- Equation name is '~27~1', location is LC1_A3, type is buried.
-- synthesized logic cell
!_LC1_A3 = _LC1_A3~NOT;
_LC1_A3~NOT = LCELL( _EQ001);
_EQ001 = minute3
# minute2
# minute1
# minute0;
-- Node name is '~27~2'
-- Equation name is '~27~2', location is LC1_C11, type is buried.
-- synthesized logic cell
!_LC1_C11 = _LC1_C11~NOT;
_LC1_C11~NOT = LCELL( _EQ002);
_EQ002 = minute7
# minute6
# minute5
# minute4;
-- Node name is '~97~1'
-- Equation name is '~97~1', location is LC3_B9, type is buried.
-- synthesized logic cell
_LC3_B9 = LCELL( _EQ003);
_EQ003 = hour0 & !hour2 & !_LC1_B3 & !second1;
-- Node name is '~116~1'
-- Equation name is '~116~1', location is LC3_B3, type is buried.
-- synthesized logic cell
!_LC3_B3 = _LC3_B3~NOT;
_LC3_B3~NOT = LCELL( _EQ004);
_EQ004 = !hour5 & !_LC2_B3;
-- Node name is '~116~2'
-- Equation name is '~116~2', location is LC1_B9, type is buried.
-- synthesized logic cell
!_LC1_B9 = _LC1_B9~NOT;
_LC1_B9~NOT = LCELL( _EQ005);
_EQ005 = !hour1 & hour2 & hour4 & !_LC3_B3
# hour1 & !hour2 & !hour4 & !_LC3_B3;
-- Node name is '~221~1'
-- Equation name is '~221~1', location is LC7_B9, type is buried.
-- synthesized logic cell
_LC7_B9 = LCELL( _EQ006);
_EQ006 = hour0 & !_LC1_B9 & !second1
# hour0 & !_LC1_B9 & !second2;
-- Node name is ':240'
-- Equation name is '_LC6_B9', type is buried
_LC6_B9 = LCELL( _EQ007);
_EQ007 = !hour0 & hour2 & !_LC1_B3;
-- Node name is '~364~1'
-- Equation name is '~364~1', location is LC8_B3, type is buried.
-- synthesized logic cell
!_LC8_B3 = _LC8_B3~NOT;
_LC8_B3~NOT = LCELL( _EQ008);
_EQ008 = !hour1 & !hour2 & hour3 & hour4
# hour1 & hour2 & !hour3 & !hour4;
-- Node name is '~364~2'
-- Equation name is '~364~2', location is LC5_B3, type is buried.
-- synthesized logic cell
!_LC5_B3 = _LC5_B3~NOT;
_LC5_B3~NOT = LCELL( _EQ009);
_EQ009 = !hour5 & !hour6 & !hour7 & !_LC8_B3;
-- Node name is ':382'
-- Equation name is '_LC4_B2', type is buried
_LC4_B2 = LCELL( _EQ010);
_EQ010 = _LC2_B7 & !second1;
-- Node name is '~407~1'
-- Equation name is '~407~1', location is LC5_B2, type is buried.
-- synthesized logic cell
_LC5_B2 = LCELL( _EQ011);
_EQ011 = !hour0 & _LC4_B2 & !_LC5_B3
# !hour0 & !_LC5_B3 & !second4;
-- Node name is ':444'
-- Equation name is '_LC2_B7', type is buried
_LC2_B7 = LCELL( _EQ012);
_EQ012 = !second2 & !second3;
-- Node name is '~469~1'
-- Equation name is '~469~1', location is LC3_B2, type is buried.
-- synthesized logic cell
_LC3_B2 = LCELL( _EQ013);
_EQ013 = hour0 & !_LC5_B3 & !second4
# hour0 & _LC2_B7 & !_LC5_B3;
-- Node name is '~488~1'
-- Equation name is '~488~1', location is LC7_B3, type is buried.
-- synthesized logic cell
!_LC7_B3 = _LC7_B3~NOT;
_LC7_B3~NOT = LCELL( _EQ014);
_EQ014 = !hour1 & hour3 & !hour4 & !hour5
# !hour1 & !hour3 & !hour4 & hour5;
-- Node name is '~488~2'
-- Equation name is '~488~2', location is LC6_B3, type is buried.
-- synthesized logic cell
!_LC6_B3 = _LC6_B3~NOT;
_LC6_B3~NOT = LCELL( _EQ015);
_EQ015 = !hour2 & !hour6 & !hour7 & !_LC7_B3;
-- Node name is ':504'
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