📄 _2to1mux.rpt
字号:
- 6 - C 23 OR2 3 0 1 0 :42
- 4 - C 23 OR2 3 0 1 0 :46
- 7 - C 23 OR2 3 0 1 0 :50
- 3 - C 23 OR2 3 0 1 0 :54
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\workhard\_2to1mux.rpt
_2to1mux
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 1/ 96( 1%) 0/ 48( 0%) 1/ 48( 2%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
C: 6/ 96( 6%) 0/ 48( 0%) 8/ 48( 16%) 6/16( 37%) 3/16( 18%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\workhard\_2to1mux.rpt
_2to1mux
** EQUATIONS **
SEL : INPUT;
X0 : INPUT;
X1 : INPUT;
X2 : INPUT;
X3 : INPUT;
X4 : INPUT;
X5 : INPUT;
X6 : INPUT;
X7 : INPUT;
Y0 : INPUT;
Y1 : INPUT;
Y2 : INPUT;
Y3 : INPUT;
Y4 : INPUT;
Y5 : INPUT;
Y6 : INPUT;
Y7 : INPUT;
-- Node name is 'OUT0'
-- Equation name is 'OUT0', type is output
OUT0 = _LC3_C23;
-- Node name is 'OUT1'
-- Equation name is 'OUT1', type is output
OUT1 = _LC7_C23;
-- Node name is 'OUT2'
-- Equation name is 'OUT2', type is output
OUT2 = _LC4_C23;
-- Node name is 'OUT3'
-- Equation name is 'OUT3', type is output
OUT3 = _LC6_C23;
-- Node name is 'OUT4'
-- Equation name is 'OUT4', type is output
OUT4 = _LC2_C23;
-- Node name is 'OUT5'
-- Equation name is 'OUT5', type is output
OUT5 = _LC5_C23;
-- Node name is 'OUT6'
-- Equation name is 'OUT6', type is output
OUT6 = _LC1_C23;
-- Node name is 'OUT7'
-- Equation name is 'OUT7', type is output
OUT7 = _LC8_C23;
-- Node name is ':26'
-- Equation name is '_LC8_C23', type is buried
_LC8_C23 = LCELL( _EQ001);
_EQ001 = SEL & X7
# !SEL & Y7;
-- Node name is ':30'
-- Equation name is '_LC1_C23', type is buried
_LC1_C23 = LCELL( _EQ002);
_EQ002 = SEL & X6
# !SEL & Y6;
-- Node name is ':34'
-- Equation name is '_LC5_C23', type is buried
_LC5_C23 = LCELL( _EQ003);
_EQ003 = SEL & X5
# !SEL & Y5;
-- Node name is ':38'
-- Equation name is '_LC2_C23', type is buried
_LC2_C23 = LCELL( _EQ004);
_EQ004 = SEL & X4
# !SEL & Y4;
-- Node name is ':42'
-- Equation name is '_LC6_C23', type is buried
_LC6_C23 = LCELL( _EQ005);
_EQ005 = SEL & X3
# !SEL & Y3;
-- Node name is ':46'
-- Equation name is '_LC4_C23', type is buried
_LC4_C23 = LCELL( _EQ006);
_EQ006 = SEL & X2
# !SEL & Y2;
-- Node name is ':50'
-- Equation name is '_LC7_C23', type is buried
_LC7_C23 = LCELL( _EQ007);
_EQ007 = SEL & X1
# !SEL & Y1;
-- Node name is ':54'
-- Equation name is '_LC3_C23', type is buried
_LC3_C23 = LCELL( _EQ008);
_EQ008 = SEL & X0
# !SEL & Y0;
Project Information f:\workhard\_2to1mux.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 12,754K
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