4位等值比较器.vhd

清华大学Altera FPGA工程师成长手册（光盘视频）

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;                		//定义实体comp4
ENTITY comp4 IS
    PORT(a, b:   IN STD_LOGIC_VECTOR(3 downto 0);	//a, b都是4位标准逻辑信号，作为输入
            y:  OUT STD_LOGIC);                  		//y是1位标准逻辑信号，作为输出
END comp4; 								//结构体 1：该结构体采用IF语句描述4位等值比										//较器设计
ARCHITECTURE  behavior  OF  comp4  IS            	//结构体名是behavior
BEGIN
Comp: PROCESS(a,b)
      BEGIN
         IF a=b THEN
             y<='1';
         ELSE
             y<='0';
         END  IF;
     END PROCESS comp;
END  behavior;									//结构体 2：该结构体采用条件赋值语句描述4位												//值比较器设计
ARCHITECTURE  dataflow  OF  comp4  IS         		//结构体名是dataflow
BEGIN
         y<='1'  WHEN(a=b)  ELSE  '0';
END  dataflow;								//结构体 3：该结构体采用结构化方法描述4位等												//值比较器设计
ARCHITECTURE  structural  OF  comp4  IS       		//结构体名是structural
        COMPONENT xnor2
              PORT(in1,in2:  IN STD_LOGIC;
                         Out: OUT STD_LOGIC);
         END COMPONENT;
         COMPONENT and4
               PORT(in1, in2, in3, in4: IN STD_LOGIC;
                           Out: OUT STD-LOGIC);
          END COMPONENT;
          SIGNAL s: STD_LOGIC_VECTOR(0 to 3);
BEGIN
      u0: xnor2 PORT MAP(a(0),b(0),s(0));
      u1: xnor2 PORT MAP(a(1),b(1),s(1));
      u2: xnor2 PORT MAP(a(2),b(2),s(2));
      u3: xnor2 PORT MAP(a(3),b(3),s(3));
      u4: and4  PORT MAP(s(0),s(1),s(2),s(3),y);
END  structural;
											//配置程序 
CONFIGURATION  comp4_con  OF  comp4  IS  		//comp4_con是配置名
       FOR  behavior                           		//指定为comp4_con配置的结构体是behavior
       END  FOR;
END  comp4_con;