songer.tan.qmsg

乐曲演奏设计电路,可演奏不同的乐曲.长时间播放音乐.

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk8hz 120 " "Warning: Circuit may not operate. Detected 120 non-operational path(s) clocked by clock \"clk8hz\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|ram_block3a1~porta_address_reg0 tonetaba:u2\|tone\[3\] clk8hz 5.14 ns " "Info: Found hold time violation between source  pin or register \"notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|ram_block3a1~porta_address_reg0\" and destination pin or register \"tonetaba:u2\|tone\[3\]\" for clock \"clk8hz\" (Hold time is 5.14 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "11.968 ns + Largest " "Info: + Largest clock skew is 11.968 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk8hz destination 14.921 ns + Longest register " "Info: + Longest clock path from clock \"clk8hz\" to destination register is 14.921 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk8hz 1 CLK PIN_29 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 25; CLK Node = 'clk8hz'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk8hz } "NODE_NAME" } } { "songer.vhd" "" { Text "F:/EDA AND VHDL/SONGER/songer.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(1.372 ns) 3.603 ns notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|ram_block3a1~porta_address_reg7 2 MEM M4K_X17_Y10 4 " "Info: 2: + IC(0.762 ns) + CELL(1.372 ns) = 3.603 ns; Loc. = M4K_X17_Y10; Fanout = 4; MEM Node = 'notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|ram_block3a1~porta_address_reg7'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.134 ns" { clk8hz notetabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_el51:auto_generated|altsyncram_ldj2:altsyncram1|ram_block3a1~porta_address_reg7 } "NODE_NAME" } } { "db/altsyncram_ldj2.tdf" "" { Text "F:/EDA AND VHDL/SONGER/db/altsyncram_ldj2.tdf" 80 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.308 ns) 7.911 ns notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|q_a\[2\] 3 MEM M4K_X17_Y10 12 " "Info: 3: + IC(0.000 ns) + CELL(4.308 ns) = 7.911 ns; Loc. = M4K_X17_Y10; Fanout = 12; MEM Node = 'notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|q_a\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.308 ns" { notetabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_el51:auto_generated|altsyncram_ldj2:altsyncram1|ram_block3a1~porta_address_reg7 notetabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_el51:auto_generated|altsyncram_ldj2:altsyncram1|q_a[2] } "NODE_NAME" } } { "db/altsyncram_ldj2.tdf" "" { Text "F:/EDA AND VHDL/SONGER/db/altsyncram_ldj2.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.169 ns) + CELL(0.590 ns) 9.670 ns tonetaba:u2\|Mux4~31 4 COMB LC_X19_Y10_N1 15 " "Info: 4: + IC(1.169 ns) + CELL(0.590 ns) = 9.670 ns; Loc. = LC_X19_Y10_N1; Fanout = 15; COMB Node = 'tonetaba:u2\|Mux4~31'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.759 ns" { notetabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_el51:auto_generated|altsyncram_ldj2:altsyncram1|q_a[2] tonetaba:u2|Mux4~31 } "NODE_NAME" } } { "tonetaba.vhd" "" { Text "F:/EDA AND VHDL/SONGER/tonetaba.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.137 ns) + CELL(0.114 ns) 14.921 ns tonetaba:u2\|tone\[3\] 5 REG LC_X19_Y10_N5 1 " "Info: 5: + IC(5.137 ns) + CELL(0.114 ns) = 14.921 ns; Loc. = LC_X19_Y10_N5; Fanout = 1; REG Node = 'tonetaba:u2\|tone\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.251 ns" { tonetaba:u2|Mux4~31 tonetaba:u2|tone[3] } "NODE_NAME" } } { "tonetaba.vhd" "" { Text "F:/EDA AND VHDL/SONGER/tonetaba.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.853 ns ( 52.63 % ) " "Info: Total cell delay = 7.853 ns ( 52.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.068 ns ( 47.37 % ) " "Info: Total interconnect delay = 7.068 ns ( 47.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/