📄 songer.tan.qmsg
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk12mh register speakera:u3\|\\genspks:count11\[3\] register speakera:u3\|\\genspks:count11\[4\] 195.69 MHz 5.11 ns Internal " "Info: Clock \"clk12mh\" has Internal fmax of 195.69 MHz between source register \"speakera:u3\|\\genspks:count11\[3\]\" and destination register \"speakera:u3\|\\genspks:count11\[4\]\" (period= 5.11 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.647 ns + Longest register register " "Info: + Longest register to register delay is 4.647 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns speakera:u3\|\\genspks:count11\[3\] 1 REG LC_X22_Y12_N8 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y12_N8; Fanout = 4; REG Node = 'speakera:u3\|\\genspks:count11\[3\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { speakera:u3|\genspks:count11[3] } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.283 ns) + CELL(0.590 ns) 1.873 ns speakera:u3\|Equal0~100 2 COMB LC_X22_Y11_N6 2 " "Info: 2: + IC(1.283 ns) + CELL(0.590 ns) = 1.873 ns; Loc. = LC_X22_Y11_N6; Fanout = 2; COMB Node = 'speakera:u3\|Equal0~100'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.873 ns" { speakera:u3|\genspks:count11[3] speakera:u3|Equal0~100 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 2.169 ns speakera:u3\|Equal0~103 3 COMB LC_X22_Y11_N7 11 " "Info: 3: + IC(0.182 ns) + CELL(0.114 ns) = 2.169 ns; Loc. = LC_X22_Y11_N7; Fanout = 11; COMB Node = 'speakera:u3\|Equal0~103'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.296 ns" { speakera:u3|Equal0~100 speakera:u3|Equal0~103 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.253 ns) + CELL(1.225 ns) 4.647 ns speakera:u3\|\\genspks:count11\[4\] 4 REG LC_X22_Y12_N9 3 " "Info: 4: + IC(1.253 ns) + CELL(1.225 ns) = 4.647 ns; Loc. = LC_X22_Y12_N9; Fanout = 3; REG Node = 'speakera:u3\|\\genspks:count11\[4\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.478 ns" { speakera:u3|Equal0~103 speakera:u3|\genspks:count11[4] } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.929 ns ( 41.51 % ) " "Info: Total cell delay = 1.929 ns ( 41.51 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.718 ns ( 58.49 % ) " "Info: Total interconnect delay = 2.718 ns ( 58.49 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.647 ns" { speakera:u3|\genspks:count11[3] speakera:u3|Equal0~100 speakera:u3|Equal0~103 speakera:u3|\genspks:count11[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.647 ns" { speakera:u3|\genspks:count11[3] speakera:u3|Equal0~100 speakera:u3|Equal0~103 speakera:u3|\genspks:count11[4] } { 0.000ns 1.283ns 0.182ns 1.253ns } { 0.000ns 0.590ns 0.114ns 1.225ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.202 ns - Smallest " "Info: - Smallest clock skew is -0.202 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk12mh destination 7.988 ns + Shortest register " "Info: + Shortest clock path from clock \"clk12mh\" to destination register is 7.988 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk12mh 1 CLK PIN_28 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 4; CLK Node = 'clk12mh'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk12mh } "NODE_NAME" } } { "songer.vhd" "" { Text "F:/EDA AND VHDL/SONGER/songer.vhd" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.935 ns) 3.166 ns speakera:u3\|\\divideclk:count4\[3\] 2 REG LC_X27_Y10_N6 2 " "Info: 2: + IC(0.762 ns) + CELL(0.935 ns) = 3.166 ns; Loc. = LC_X27_Y10_N6; Fanout = 2; REG Node = 'speakera:u3\|\\divideclk:count4\[3\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.697 ns" { clk12mh speakera:u3|\divideclk:count4[3] } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.529 ns) + CELL(0.114 ns) 3.809 ns speakera:u3\|LessThan0~39 3 COMB LC_X27_Y10_N5 16 " "Info: 3: + IC(0.529 ns) + CELL(0.114 ns) = 3.809 ns; Loc. = LC_X27_Y10_N5; Fanout = 16; COMB Node = 'speakera:u3\|LessThan0~39'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.643 ns" { speakera:u3|\divideclk:count4[3] speakera:u3|LessThan0~39 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1657 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.468 ns) + CELL(0.711 ns) 7.988 ns speakera:u3\|\\genspks:count11\[4\] 4 REG LC_X22_Y12_N9 3 " "Info: 4: + IC(3.468 ns) + CELL(0.711 ns) = 7.988 ns; Loc. = LC_X22_Y12_N9; Fanout = 3; REG Node = 'speakera:u3\|\\genspks:count11\[4\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.179 ns" { speakera:u3|LessThan0~39 speakera:u3|\genspks:count11[4] } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.229 ns ( 40.42 % ) " "Info: Total cell delay = 3.229 ns ( 40.42 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.759 ns ( 59.58 % ) " "Info: Total interconnect delay = 4.759 ns ( 59.58 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.988 ns" { clk12mh speakera:u3|\divideclk:count4[3] speakera:u3|LessThan0~39 speakera:u3|\genspks:count11[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.988 ns" { clk12mh clk12mh~out0 speakera:u3|\divideclk:count4[3] speakera:u3|LessThan0~39 speakera:u3|\genspks:count11[4] } { 0.000ns 0.000ns 0.762ns 0.529ns 3.468ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk12mh source 8.190 ns - Longest register " "Info: - Longest clock path from clock \"clk12mh\" to source register is 8.190 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk12mh 1 CLK PIN_28 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 4; CLK Node = 'clk12mh'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk12mh } "NODE_NAME" } } { "songer.vhd" "" { Text "F:/EDA AND VHDL/SONGER/songer.vhd" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.935 ns) 3.166 ns speakera:u3\|\\divideclk:count4\[2\] 2 REG LC_X27_Y10_N2 3 " "Info: 2: + IC(0.762 ns) + CELL(0.935 ns) = 3.166 ns; Loc. = LC_X27_Y10_N2; Fanout = 3; REG Node = 'speakera:u3\|\\divideclk:count4\[2\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.697 ns" { clk12mh speakera:u3|\divideclk:count4[2] } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.553 ns) + CELL(0.292 ns) 4.011 ns speakera:u3\|LessThan0~39 3 COMB LC_X27_Y10_N5 16 " "Info: 3: + IC(0.553 ns) + CELL(0.292 ns) = 4.011 ns; Loc. = LC_X27_Y10_N5; Fanout = 16; COMB Node = 'speakera:u3\|LessThan0~39'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.845 ns" { speakera:u3|\divideclk:count4[2] speakera:u3|LessThan0~39 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1657 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.468 ns) + CELL(0.711 ns) 8.190 ns speakera:u3\|\\genspks:count11\[3\] 4 REG LC_X22_Y12_N8 4 " "Info: 4: + IC(3.468 ns) + CELL(0.711 ns) = 8.190 ns; Loc. = LC_X22_Y12_N8; Fanout = 4; REG Node = 'speakera:u3\|\\genspks:count11\[3\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.179 ns" { speakera:u3|LessThan0~39 speakera:u3|\genspks:count11[3] } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.407 ns ( 41.60 % ) " "Info: Total cell delay = 3.407 ns ( 41.60 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.783 ns ( 58.40 % ) " "Info: Total interconnect delay = 4.783 ns ( 58.40 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.190 ns" { clk12mh speakera:u3|\divideclk:count4[2] speakera:u3|LessThan0~39 speakera:u3|\genspks:count11[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.190 ns" { clk12mh clk12mh~out0 speakera:u3|\divideclk:count4[2] speakera:u3|LessThan0~39 speakera:u3|\genspks:count11[3] } { 0.000ns 0.000ns 0.762ns 0.553ns 3.468ns } { 0.000ns 1.469ns 0.935ns 0.292ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.988 ns" { clk12mh speakera:u3|\divideclk:count4[3] speakera:u3|LessThan0~39 speakera:u3|\genspks:count11[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.988 ns" { clk12mh clk12mh~out0 speakera:u3|\divideclk:count4[3] speakera:u3|LessThan0~39 speakera:u3|\genspks:count11[4] } { 0.000ns 0.000ns 0.762ns 0.529ns 3.468ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.190 ns" { clk12mh speakera:u3|\divideclk:count4[2] speakera:u3|LessThan0~39 speakera:u3|\genspks:count11[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.190 ns" { clk12mh clk12mh~out0 speakera:u3|\divideclk:count4[2] speakera:u3|LessThan0~39 speakera:u3|\genspks:count11[3] } { 0.000ns 0.000ns 0.762ns 0.553ns 3.468ns } { 0.000ns 1.469ns 0.935ns 0.292ns 0.711ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.647 ns" { speakera:u3|\genspks:count11[3] speakera:u3|Equal0~100 speakera:u3|Equal0~103 speakera:u3|\genspks:count11[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.647 ns" { speakera:u3|\genspks:count11[3] speakera:u3|Equal0~100 speakera:u3|Equal0~103 speakera:u3|\genspks:count11[4] } { 0.000ns 1.283ns 0.182ns 1.253ns } { 0.000ns 0.590ns 0.114ns 1.225ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.988 ns" { clk12mh speakera:u3|\divideclk:count4[3] speakera:u3|LessThan0~39 speakera:u3|\genspks:count11[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.988 ns" { clk12mh clk12mh~out0 speakera:u3|\divideclk:count4[3] speakera:u3|LessThan0~39 speakera:u3|\genspks:count11[4] } { 0.000ns 0.000ns 0.762ns 0.529ns 3.468ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.190 ns" { clk12mh speakera:u3|\divideclk:count4[2] speakera:u3|LessThan0~39 speakera:u3|\genspks:count11[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.190 ns" { clk12mh clk12mh~out0 speakera:u3|\divideclk:count4[2] speakera:u3|LessThan0~39 speakera:u3|\genspks:count11[3] } { 0.000ns 0.000ns 0.762ns 0.553ns 3.468ns } { 0.000ns 1.469ns 0.935ns 0.292ns 0.711ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk8hz memory notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|ram_block3a1~porta_datain_reg0 memory notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|ram_block3a1~porta_memory_reg0 197.01 MHz 5.076 ns Internal " "Info: Clock \"clk8hz\" has Internal fmax of 197.01 MHz between source memory \"notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|ram_block3a1~porta_datain_reg0\" and destination memory \"notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|ram_block3a1~porta_memory_reg0\" (period= 5.076 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.319 ns + Longest memory memory " "Info: + Longest memory to memory delay is 4.319 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|ram_block3a1~porta_datain_reg0 1 MEM M4K_X17_Y10 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X17_Y10; Fanout = 1; MEM Node = 'notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|ram_block3a1~porta_datain_reg0'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { notetabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_el51:auto_generated|altsyncram_ldj2:altsyncram1|ram_block3a1~porta_datain_reg0 } "NODE_NAME" } } { "db/altsyncram_ldj2.tdf" "" { Text "F:/EDA AND VHDL/SONGER/db/altsyncram_ldj2.tdf" 80 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.319 ns) 4.319 ns notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|ram_block3a1~porta_memory_reg0 2 MEM M4K_X17_Y10 0 " "Info: 2: + IC(0.000 ns) + CELL(4.319 ns) = 4.319 ns; Loc. = M4K_X17_Y10; Fanout = 0; MEM Node = 'notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|ram_block3a1~porta_memory_reg0'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.319 ns" { notetabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_el51:auto_generated|altsyncram_ldj2:altsyncram1|ram_block3a1~porta_datain_reg0 notetabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_el51:auto_generated|altsyncram_ldj2:altsyncram1|ram_block3a1~porta_memory_reg0 } "NODE_NAME" } } { "db/altsyncram_ldj2.tdf" "" { Text "F:/EDA AND VHDL/SONGER/db/altsyncram_ldj2.tdf" 80 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.319 ns ( 100.00 % ) " "Info: Total cell delay = 4.319 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.319 ns" { notetabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_el51:auto_generated|altsyncram_ldj2:altsyncram1|ram_block3a1~porta_datain_reg0 notetabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_el51:auto_generated|altsyncram_ldj2:altsyncram1|ram_block3a1~porta_memory_reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.319 ns" { notetabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_el51:auto_generated|altsyncram_ldj2:altsyncram1|ram_block3a1~porta_datain_reg0 notetabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_el51:auto_generated|altsyncram_ldj2:altsyncram1|ram_block3a1~porta_memory_reg0 } { 0.000ns 0.000ns } { 0.000ns 4.319ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.014 ns - Smallest " "Info: - Smallest clock skew is -0.014 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk8hz destination 2.939 ns + Shortest memory " "Info: + Shortest clock path from clock \"clk8hz\" to destination memory is 2.939 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk8hz 1 CLK PIN_29 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 25; CLK Node = 'clk8hz'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk8hz } "NODE_NAME" } } { "songer.vhd" "" { Text "F:/EDA AND VHDL/SONGER/songer.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.708 ns) 2.939 ns notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|ram_block3a1~porta_memory_reg0 2 MEM M4K_X17_Y10 0 " "Info: 2: + IC(0.762 ns) + CELL(0.708 ns) = 2.939 ns; Loc. = M4K_X17_Y10; Fanout = 0; MEM Node = 'notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|ram_block3a1~porta_memory_reg0'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.470 ns" { clk8hz notetabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_el51:auto_generated|altsyncram_ldj2:altsyncram1|ram_block3a1~porta_memory_reg0 } "NODE_NAME" } } { "db/altsyncram_ldj2.tdf" "" { Text "F:/EDA AND VHDL/SONGER/db/altsyncram_ldj2.tdf" 80 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.177 ns ( 74.07 % ) " "Info: Total cell delay = 2.177 ns ( 74.07 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.762 ns ( 25.93 % ) " "Info: Total interconnect delay = 0.762 ns ( 25.93 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.939 ns" { clk8hz notetabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_el51:auto_generated|altsyncram_ldj2:altsyncram1|ram_block3a1~porta_memory_reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.939 ns" { clk8hz clk8hz~out0 notetabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_el51:auto_generated|altsyncram_ldj2:altsyncram1|ram_block3a1~porta_memory_reg0 } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.708ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk8hz source 2.953 ns - Longest memory " "Info: - Longest clock path from clock \"clk8hz\" to source memory is 2.953 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk8hz 1 CLK PIN_29 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 25; CLK Node = 'clk8hz'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk8hz } "NODE_NAME" } } { "songer.vhd" "" { Text "F:/EDA AND VHDL/SONGER/songer.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.722 ns) 2.953 ns notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|ram_block3a1~porta_datain_reg0 2 MEM M4K_X17_Y10 1 " "Info: 2: + IC(0.762 ns) + CELL(0.722 ns) = 2.953 ns; Loc. = M4K_X17_Y10; Fanout = 1; MEM Node = 'notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|ram_block3a1~porta_datain_reg0'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.484 ns" { clk8hz notetabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_el51:auto_generated|altsyncram_ldj2:altsyncram1|ram_block3a1~porta_datain_reg0 } "NODE_NAME" } } { "db/altsyncram_ldj2.tdf" "" { Text "F:/EDA AND VHDL/SONGER/db/altsyncram_ldj2.tdf" 80 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns ( 74.20 % ) " "Info: Total cell delay = 2.191 ns ( 74.20 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.762 ns ( 25.80 % ) " "Info: Total interconnect delay = 0.762 ns ( 25.80 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.953 ns" { clk8hz notetabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_el51:auto_generated|altsyncram_ldj2:altsyncram1|ram_block3a1~porta_datain_reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.953 ns" { clk8hz clk8hz~out0 notetabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_el51:auto_generated|altsyncram_ldj2:altsyncram1|ram_block3a1~porta_datain_reg0 } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.722ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.939 ns" { clk8hz notetabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_el51:auto_generated|altsyncram_ldj2:altsyncram1|ram_block3a1~porta_memory_reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.939 ns" { clk8hz clk8hz~out0 notetabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_el51:auto_generated|altsyncram_ldj2:altsyncram1|ram_block3a1~porta_memory_reg0 } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.708ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.953 ns" { clk8hz notetabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_el51:auto_generated|altsyncram_ldj2:altsyncram1|ram_block3a1~porta_datain_reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.953 ns" { clk8hz clk8hz~out0 notetabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_el51:auto_generated|altsyncram_ldj2:altsyncram1|ram_block3a1~porta_datain_reg0 } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.722ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" { } { { "db/altsyncram_ldj2.tdf" "" { Text "F:/EDA AND VHDL/SONGER/db/altsyncram_ldj2.tdf" 80 2 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns + " "Info: + Micro setup delay of destination is 0.093 ns" { } { { "db/altsyncram_ldj2.tdf" "" { Text "F:/EDA AND VHDL/SONGER/db/altsyncram_ldj2.tdf" 80 2 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.319 ns" { notetabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_el51:auto_generated|altsyncram_ldj2:altsyncram1|ram_block3a1~porta_datain_reg0 notetabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_el51:auto_generated|altsyncram_ldj2:altsyncram1|ram_block3a1~porta_memory_reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.319 ns" { notetabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_el51:auto_generated|altsyncram_ldj2:altsyncram1|ram_block3a1~porta_datain_reg0 notetabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_el51:auto_generated|altsyncram_ldj2:altsyncram1|ram_block3a1~porta_memory_reg0 } { 0.000ns 0.000ns } { 0.000ns 4.319ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.939 ns" { clk8hz notetabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_el51:auto_generated|altsyncram_ldj2:altsyncram1|ram_block3a1~porta_memory_reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.939 ns" { clk8hz clk8hz~out0 notetabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_el51:auto_generated|altsyncram_ldj2:altsyncram1|ram_block3a1~porta_memory_reg0 } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.708ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.953 ns" { clk8hz notetabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_el51:auto_generated|altsyncram_ldj2:altsyncram1|ram_block3a1~porta_datain_reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.953 ns" { clk8hz clk8hz~out0 notetabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_el51:auto_generated|altsyncram_ldj2:altsyncram1|ram_block3a1~porta_datain_reg0 } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.722ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[1\] register sld_hub:sld_hub_inst\|hub_tdo 139.35 MHz 7.176 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 139.35 MHz between source register \"sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[1\]\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo\" (period= 7.176 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.295 ns + Longest register register " "Info: + Longest register to register delay is 3.295 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[1\] 1 REG LC_X20_Y10_N3 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y10_N3; Fanout = 4; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[1\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_dffex.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.277 ns) + CELL(0.442 ns) 1.719 ns sld_hub:sld_hub_inst\|hub_tdo~545 2 COMB LC_X20_Y9_N1 1 " "Info: 2: + IC(1.277 ns) + CELL(0.442 ns) = 1.719 ns; Loc. = LC_X20_Y9_N1; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~545'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.719 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] sld_hub:sld_hub_inst|hub_tdo~545 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.441 ns) + CELL(0.114 ns) 2.274 ns sld_hub:sld_hub_inst\|hub_tdo~546 3 COMB LC_X20_Y9_N5 1 " "Info: 3: + IC(0.441 ns) + CELL(0.114 ns) = 2.274 ns; Loc. = LC_X20_Y9_N5; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~546'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.555 ns" { sld_hub:sld_hub_inst|hub_tdo~545 sld_hub:sld_hub_inst|hub_tdo~546 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.414 ns) + CELL(0.607 ns) 3.295 ns sld_hub:sld_hub_inst\|hub_tdo 4 REG LC_X20_Y9_N3 1 " "Info: 4: + IC(0.414 ns) + CELL(0.607 ns) = 3.295 ns; Loc. = LC_X20_Y9_N3; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.021 ns" { sld_hub:sld_hub_inst|hub_tdo~546 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.163 ns ( 35.30 % ) " "Info: Total cell delay = 1.163 ns ( 35.30 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.132 ns ( 64.70 % ) " "Info: Total interconnect delay = 2.132 ns ( 64.70 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.295 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] sld_hub:sld_hub_inst|hub_tdo~545 sld_hub:sld_hub_inst|hub_tdo~546 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.295 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] sld_hub:sld_hub_inst|hub_tdo~545 sld_hub:sld_hub_inst|hub_tdo~546 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.277ns 0.441ns 0.414ns } { 0.000ns 0.442ns 0.114ns 0.607ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.032 ns - Smallest " "Info: - Smallest clock skew is -0.032 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.280 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.280 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N1 117 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 117; CLK Node = 'altera_internal_jtag~TCKUTAP'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.569 ns) + CELL(0.711 ns) 5.280 ns sld_hub:sld_hub_inst\|hub_tdo 2 REG LC_X20_Y9_N3 1 " "Info: 2: + IC(4.569 ns) + CELL(0.711 ns) = 5.280 ns; Loc. = LC_X20_Y9_N3; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.280 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 13.47 % ) " "Info: Total cell delay = 0.711 ns ( 13.47 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.569 ns ( 86.53 % ) " "Info: Total interconnect delay = 4.569 ns ( 86.53 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.280 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.280 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.569ns } { 0.000ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 5.312 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 5.312 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N1 117 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 117; CLK Node = 'altera_internal_jtag~TCKUTAP'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.601 ns) + CELL(0.711 ns) 5.312 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[1\] 2 REG LC_X20_Y10_N3 4 " "Info: 2: + IC(4.601 ns) + CELL(0.711 ns) = 5.312 ns; Loc. = LC_X20_Y10_N3; Fanout = 4; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[1\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.312 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_dffex.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 13.38 % ) " "Info: Total cell delay = 0.711 ns ( 13.38 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.601 ns ( 86.62 % ) " "Info: Total interconnect delay = 4.601 ns ( 86.62 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.312 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.312 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] } { 0.000ns 4.601ns } { 0.000ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.280 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.280 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.569ns } { 0.000ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.312 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.312 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] } { 0.000ns 4.601ns } { 0.000ns 0.711ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "c:/altera/quartus60/libraries/megafunctions/sld_dffex.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" { } { { "c:/altera/quartus60/libraries/megafunctions/sld_dffex.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } } } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.295 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] sld_hub:sld_hub_inst|hub_tdo~545 sld_hub:sld_hub_inst|hub_tdo~546 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.295 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] sld_hub:sld_hub_inst|hub_tdo~545 sld_hub:sld_hub_inst|hub_tdo~546 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.277ns 0.441ns 0.414ns } { 0.000ns 0.442ns 0.114ns 0.607ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.280 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.280 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.569ns } { 0.000ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.312 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.312 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] } { 0.000ns 4.601ns } { 0.000ns 0.711ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
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