songer.tan.qmsg

乐曲演奏设计电路,可演奏不同的乐曲.长时间播放音乐.

{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "tonetaba:u2\|tone\[8\] " "Warning: Node \"tonetaba:u2\|tone\[8\]\" is a latch" {  } { { "tonetaba.vhd" "" { Text "F:/EDA AND VHDL/SONGER/tonetaba.vhd" 11 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "tonetaba:u2\|tone\[7\] " "Warning: Node \"tonetaba:u2\|tone\[7\]\" is a latch" {  } { { "tonetaba.vhd" "" { Text "F:/EDA AND VHDL/SONGER/tonetaba.vhd" 11 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "tonetaba:u2\|tone\[6\] " "Warning: Node \"tonetaba:u2\|tone\[6\]\" is a latch" {  } { { "tonetaba.vhd" "" { Text "F:/EDA AND VHDL/SONGER/tonetaba.vhd" 11 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "tonetaba:u2\|tone\[5\] " "Warning: Node \"tonetaba:u2\|tone\[5\]\" is a latch" {  } { { "tonetaba.vhd" "" { Text "F:/EDA AND VHDL/SONGER/tonetaba.vhd" 11 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "tonetaba:u2\|tone\[0\] " "Warning: Node \"tonetaba:u2\|tone\[0\]\" is a latch" {  } { { "tonetaba.vhd" "" { Text "F:/EDA AND VHDL/SONGER/tonetaba.vhd" 11 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "tonetaba:u2\|tone\[1\] " "Warning: Node \"tonetaba:u2\|tone\[1\]\" is a latch" {  } { { "tonetaba.vhd" "" { Text "F:/EDA AND VHDL/SONGER/tonetaba.vhd" 11 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "tonetaba:u2\|tone\[2\] " "Warning: Node \"tonetaba:u2\|tone\[2\]\" is a latch" {  } { { "tonetaba.vhd" "" { Text "F:/EDA AND VHDL/SONGER/tonetaba.vhd" 11 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "tonetaba:u2\|tone\[3\] " "Warning: Node \"tonetaba:u2\|tone\[3\]\" is a latch" {  } { { "tonetaba.vhd" "" { Text "F:/EDA AND VHDL/SONGER/tonetaba.vhd" 11 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "tonetaba:u2\|tone\[4\] " "Warning: Node \"tonetaba:u2\|tone\[4\]\" is a latch" {  } { { "tonetaba.vhd" "" { Text "F:/EDA AND VHDL/SONGER/tonetaba.vhd" 11 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "tonetaba:u2\|tone\[9\] " "Warning: Node \"tonetaba:u2\|tone\[9\]\" is a latch" {  } { { "tonetaba.vhd" "" { Text "F:/EDA AND VHDL/SONGER/tonetaba.vhd" 11 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "tonetaba:u2\|tone\[10\] " "Warning: Node \"tonetaba:u2\|tone\[10\]\" is a latch" {  } { { "tonetaba.vhd" "" { Text "F:/EDA AND VHDL/SONGER/tonetaba.vhd" 11 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "tonetaba:u2\|code\[0\] " "Warning: Node \"tonetaba:u2\|code\[0\]\" is a latch" {  } { { "tonetaba.vhd" "" { Text "F:/EDA AND VHDL/SONGER/tonetaba.vhd" 11 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "tonetaba:u2\|code\[1\] " "Warning: Node \"tonetaba:u2\|code\[1\]\" is a latch" {  } { { "tonetaba.vhd" "" { Text "F:/EDA AND VHDL/SONGER/tonetaba.vhd" 11 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "tonetaba:u2\|code\[2\] " "Warning: Node \"tonetaba:u2\|code\[2\]\" is a latch" {  } { { "tonetaba.vhd" "" { Text "F:/EDA AND VHDL/SONGER/tonetaba.vhd" 11 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "tonetaba:u2\|high " "Warning: Node \"tonetaba:u2\|high\" is a latch" {  } { { "tonetaba.vhd" "" { Text "F:/EDA AND VHDL/SONGER/tonetaba.vhd" 6 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk12mh " "Info: Assuming node \"clk12mh\" is an undefined clock" {  } { { "songer.vhd" "" { Text "F:/EDA AND VHDL/SONGER/songer.vhd" 4 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk12mh" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk8hz " "Info: Assuming node \"clk8hz\" is an undefined clock" {  } { { "songer.vhd" "" { Text "F:/EDA AND VHDL/SONGER/songer.vhd" 5 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk8hz" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "altera_internal_jtag~TCKUTAP " "Info: Assuming node \"altera_internal_jtag~TCKUTAP\" is an undefined clock" {  } { { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TCKUTAP" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "16 " "Warning: Found 16 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "speakera:u3\|\\divideclk:count4\[3\] " "Info: Detected ripple clock \"speakera:u3\|\\divideclk:count4\[3\]\" as buffer" {  } { { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "speakera:u3\|\\divideclk:count4\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "speakera:u3\|\\divideclk:count4\[2\] " "Info: Detected ripple clock \"speakera:u3\|\\divideclk:count4\[2\]\" as buffer" {  } { { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "speakera:u3\|\\divideclk:count4\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "speakera:u3\|LessThan0~39 " "Info: Detected gated clock \"speakera:u3\|LessThan0~39\" as buffer" {  } { { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1657 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "speakera:u3\|LessThan0~39" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|ram_block3a1~porta_address_reg7 " "Info: Detected ripple clock \"notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|ram_block3a1~porta_address_reg7\" as buffer" {  } { { "db/altsyncram_ldj2.tdf" "" { Text "F:/EDA AND VHDL/SONGER/db/altsyncram_ldj2.tdf" 80 2 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|ram_block3a1~porta_address_reg7" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|ram_block3a1~porta_address_reg6 " "Info: Detected ripple clock \"notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|ram_block3a1~porta_address_reg6\" as buffer" {  } { { "db/altsyncram_ldj2.tdf" "" { Text "F:/EDA AND VHDL/SONGER/db/altsyncram_ldj2.tdf" 80 2 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|ram_block3a1~porta_address_reg6" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|ram_block3a1~porta_address_reg5 " "Info: Detected ripple clock \"notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|ram_block3a1~porta_address_reg5\" as buffer" {  } { { "db/altsyncram_ldj2.tdf" "" { Text "F:/EDA AND VHDL/SONGER/db/altsyncram_ldj2.tdf" 80 2 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|ram_block3a1~porta_address_reg5" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|ram_block3a1~porta_address_reg4 " "Info: Detected ripple clock \"notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|ram_block3a1~porta_address_reg4\" as buffer" {  } { { "db/altsyncram_ldj2.tdf" "" { Text "F:/EDA AND VHDL/SONGER/db/altsyncram_ldj2.tdf" 80 2 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|ram_block3a1~porta_address_reg4" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|ram_block3a1~porta_address_reg3 " "Info: Detected ripple clock \"notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|ram_block3a1~porta_address_reg3\" as buffer" {  } { { "db/altsyncram_ldj2.tdf" "" { Text "F:/EDA AND VHDL/SONGER/db/altsyncram_ldj2.tdf" 80 2 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|ram_block3a1~porta_address_reg3" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|ram_block3a1~porta_address_reg2 " "Info: Detected ripple clock \"notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|ram_block3a1~porta_address_reg2\" as buffer" {  } { { "db/altsyncram_ldj2.tdf" "" { Text "F:/EDA AND VHDL/SONGER/db/altsyncram_ldj2.tdf" 80 2 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|ram_block3a1~porta_address_reg2" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|ram_block3a1~porta_address_reg1 " "Info: Detected ripple clock \"notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|ram_block3a1~porta_address_reg1\" as buffer" {  } { { "db/altsyncram_ldj2.tdf" "" { Text "F:/EDA AND VHDL/SONGER/db/altsyncram_ldj2.tdf" 80 2 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|ram_block3a1~porta_address_reg1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|ram_block3a1~porta_address_reg0 " "Info: Detected ripple clock \"notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|ram_block3a1~porta_address_reg0\" as buffer" {  } { { "db/altsyncram_ldj2.tdf" "" { Text "F:/EDA AND VHDL/SONGER/db/altsyncram_ldj2.tdf" 80 2 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|ram_block3a1~porta_address_reg0" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|q_a\[0\] " "Info: Detected gated clock \"notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|q_a\[0\]\" as buffer" {  } { { "db/altsyncram_ldj2.tdf" "" { Text "F:/EDA AND VHDL/SONGER/db/altsyncram_ldj2.tdf" 43 2 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|q_a\[0\]" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|q_a\[3\] " "Info: Detected gated clock \"notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|q_a\[3\]\" as buffer" {  } { { "db/altsyncram_ldj2.tdf" "" { Text "F:/EDA AND VHDL/SONGER/db/altsyncram_ldj2.tdf" 43 2 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|q_a\[3\]" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|q_a\[2\] " "Info: Detected gated clock \"notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|q_a\[2\]\" as buffer" {  } { { "db/altsyncram_ldj2.tdf" "" { Text "F:/EDA AND VHDL/SONGER/db/altsyncram_ldj2.tdf" 43 2 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|q_a\[2\]" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|q_a\[1\] " "Info: Detected gated clock \"notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|q_a\[1\]\" as buffer" {  } { { "db/altsyncram_ldj2.tdf" "" { Text "F:/EDA AND VHDL/SONGER/db/altsyncram_ldj2.tdf" 43 2 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|altsyncram_ldj2:altsyncram1\|q_a\[1\]" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "speakera:u3\|fullspks " "Info: Detected ripple clock \"speakera:u3\|fullspks\" as buffer" {  } { { "speakera.vhd" "" { Text "F:/EDA AND VHDL/SONGER/speakera.vhd" 10 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "speakera:u3\|fullspks" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}