songer.map.qmsg

乐曲演奏设计电路,可演奏不同的乐曲.长时间播放音乐.

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_rom_sr notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:name_gen:info_rom_sr " "Info: Elaborating entity \"sld_rom_sr\" for hierarchy \"notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:name_gen:info_rom_sr\"" {  } { { "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "\\ram_rom_logic_gen:name_gen:info_rom_sr" { Text "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 635 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:name_gen:info_rom_sr notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|sld_mod_ram_rom:mgl_prim2 " "Info: Elaborated megafunction instantiation \"notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:name_gen:info_rom_sr\", which is child of megafunction instantiation \"notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|sld_mod_ram_rom:mgl_prim2\"" {  } { { "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 635 -1 0 } } { "db/altsyncram_el51.tdf" "" { Text "F:/EDA AND VHDL/SONGER/db/altsyncram_el51.tdf" 35 2 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|sld_mod_ram_rom:mgl_prim2 " "Info: Instantiated megafunction \"notetabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_el51:auto_generated\|sld_mod_ram_rom:mgl_prim2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "CVALUE 0000 " "Info: Parameter \"CVALUE\" = \"0000\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "IS_DATA_IN_RAM 1 " "Info: Parameter \"IS_DATA_IN_RAM\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "IS_READABLE 1 " "Info: Parameter \"IS_READABLE\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NODE_NAME 1380928817 " "Info: Parameter \"NODE_NAME\" = \"1380928817\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS 256 " "Info: Parameter \"NUMWORDS\" = \"256\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "SHIFT_COUNT_BITS 3 " "Info: Parameter \"SHIFT_COUNT_BITS\" = \"3\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_WORD 4 " "Info: Parameter \"WIDTH_WORD\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD 8 " "Info: Parameter \"WIDTHAD\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "db/altsyncram_el51.tdf" "" { Text "F:/EDA AND VHDL/SONGER/db/altsyncram_el51.tdf" 35 2 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tonetaba tonetaba:u2 " "Info: Elaborating entity \"tonetaba\" for hierarchy \"tonetaba:u2\"" {  } { { "songer.vhd" "u2" { Text "F:/EDA AND VHDL/SONGER/songer.vhd" 30 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "tone tonetaba.vhd(11) " "Warning (10631): VHDL Process Statement warning at tonetaba.vhd(11): inferring latch(es) for signal or variable \"tone\", which holds its previous value in one or more paths through the process" {  } { { "tonetaba.vhd" "" { Text "F:/EDA AND VHDL/SONGER/tonetaba.vhd" 11 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "code tonetaba.vhd(11) " "Warning (10631): VHDL Process Statement warning at tonetaba.vhd(11): inferring latch(es) for signal or variable \"code\", which holds its previous value in one or more paths through the process" {  } { { "tonetaba.vhd" "" { Text "F:/EDA AND VHDL/SONGER/tonetaba.vhd" 11 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "high tonetaba.vhd(11) " "Warning (10631): VHDL Process Statement warning at tonetaba.vhd(11): inferring latch(es) for signal or variable \"high\", which holds its previous value in one or more paths through the process" {  } { { "tonetaba.vhd" "" { Text "F:/EDA AND VHDL/SONGER/tonetaba.vhd" 11 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "high tonetaba.vhd(11) " "Info (10041): Verilog HDL or VHDL info at tonetaba.vhd(11): inferred latch for \"high\"" {  } { { "tonetaba.vhd" "" { Text "F:/EDA AND VHDL/SONGER/tonetaba.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "code\[0\] tonetaba.vhd(11) " "Info (10041): Verilog HDL or VHDL info at tonetaba.vhd(11): inferred latch for \"code\[0\]\"" {  } { { "tonetaba.vhd" "" { Text "F:/EDA AND VHDL/SONGER/tonetaba.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "code\[1\] tonetaba.vhd(11) " "Info (10041): Verilog HDL or VHDL info at tonetaba.vhd(11): inferred latch for \"code\[1\]\"" {  } { { "tonetaba.vhd" "" { Text "F:/EDA AND VHDL/SONGER/tonetaba.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "code\[2\] tonetaba.vhd(11) " "Info (10041): Verilog HDL or VHDL info at tonetaba.vhd(11): inferred latch for \"code\[2\]\"" {  } { { "tonetaba.vhd" "" { Text "F:/EDA AND VHDL/SONGER/tonetaba.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "code\[3\] tonetaba.vhd(11) " "Info (10041): Verilog HDL or VHDL info at tonetaba.vhd(11): inferred latch for \"code\[3\]\"" {  } { { "tonetaba.vhd" "" { Text "F:/EDA AND VHDL/SONGER/tonetaba.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "tone\[0\] tonetaba.vhd(11) " "Info (10041): Verilog HDL or VHDL info at tonetaba.vhd(11): inferred latch for \"tone\[0\]\"" {  } { { "tonetaba.vhd" "" { Text "F:/EDA AND VHDL/SONGER/tonetaba.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "tone\[1\] tonetaba.vhd(11) " "Info (10041): Verilog HDL or VHDL info at tonetaba.vhd(11): inferred latch for \"tone\[1\]\"" {  } { { "tonetaba.vhd" "" { Text "F:/EDA AND VHDL/SONGER/tonetaba.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "tone\[2\] tonetaba.vhd(11) " "Info (10041): Verilog HDL or VHDL info at tonetaba.vhd(11): inferred latch for \"tone\[2\]\"" {  } { { "tonetaba.vhd" "" { Text "F:/EDA AND VHDL/SONGER/tonetaba.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "tone\[3\] tonetaba.vhd(11) " "Info (10041): Verilog HDL or VHDL info at tonetaba.vhd(11): inferred latch for \"tone\[3\]\"" {  } { { "tonetaba.vhd" "" { Text "F:/EDA AND VHDL/SONGER/tonetaba.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "tone\[4\] tonetaba.vhd(11) " "Info (10041): Verilog HDL or VHDL info at tonetaba.vhd(11): inferred latch for \"tone\[4\]\"" {  } { { "tonetaba.vhd" "" { Text "F:/EDA AND VHDL/SONGER/tonetaba.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "tone\[5\] tonetaba.vhd(11) " "Info (10041): Verilog HDL or VHDL info at tonetaba.vhd(11): inferred latch for \"tone\[5\]\"" {  } { { "tonetaba.vhd" "" { Text "F:/EDA AND VHDL/SONGER/tonetaba.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "tone\[6\] tonetaba.vhd(11) " "Info (10041): Verilog HDL or VHDL info at tonetaba.vhd(11): inferred latch for \"tone\[6\]\"" {  } { { "tonetaba.vhd" "" { Text "F:/EDA AND VHDL/SONGER/tonetaba.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "tone\[7\] tonetaba.vhd(11) " "Info (10041): Verilog HDL or VHDL info at tonetaba.vhd(11): inferred latch for \"tone\[7\]\"" {  } { { "tonetaba.vhd" "" { Text "F:/EDA AND VHDL/SONGER/tonetaba.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "tone\[8\] tonetaba.vhd(11) " "Info (10041): Verilog HDL or VHDL info at tonetaba.vhd(11): inferred latch for \"tone\[8\]\"" {  } { { "tonetaba.vhd" "" { Text "F:/EDA AND VHDL/SONGER/tonetaba.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "tone\[9\] tonetaba.vhd(11) " "Info (10041): Verilog HDL or VHDL info at tonetaba.vhd(11): inferred latch for \"tone\[9\]\"" {  } { { "tonetaba.vhd" "" { Text "F:/EDA AND VHDL/SONGER/tonetaba.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}