sdp2005.abl.txt

LSI2005开发板及芯片资料。主芯片为sc2005

"------------------------------------------------------------------------------"
" Internal registers
"------------------------------------------------------------------------------"
" Write to SW Reset Register
ETHRDIS       :=  AD2;
LNKDIS        :=  AD1;
STATEN        :=  AD0;

SWRSTR.CLK     = !(RCK & SWRESET);
SWRSTR.AR      =  RESET;

" Write to Control Register
XPTSEL        :=  AD3;  " modified for SDP2005
AUXPAR        :=  AD2;
LNKEX         :=  AD1;
LNKOT         :=  AD0;

CTRLR.CLK      = !(RCK & CTRL);
CTRLR.AR       =  RESET;

" Write to FP Control Register
CPUALIVE      :=  AD2;
KPDWR1        :=  AD1;
KPDWR0        :=  AD0;		

FPCTRLR.CLK    = !(RCK & FPCTRL);
FPCTRLR.AR     =  RESET;

" Write to Interrupt Mask  Register
I1394MSK      :=  AD1;
ATAINTMSK     :=  AD0;

INTMASKR.CLK   = !(RCK & INTMASK);
INTMASKR.AR    =  RESET;

" Reset of Status Registers
"STAT1D.AR     =  RESET # STATEN;
STAT2R.AR      =  RESET # STATEN;

" Read from registers
DATA           = (PLD_VER & VERSION)              " Version register
               # (CTRLD & CTRL)                   " Control register
               # (FPCTRLD & FPCTRL)               " FP Control register
               # (INTMASKD & INTMASK)             " Interrupt Mask register
               # (STAT1D & STATUS1)               " Status register 1
               # (STAT2D & STATUS2)               " Status register 2
               # (STAT3D & STATUS3);              " Status register 3

DATA.OE        = !CSN2 & BRDCTRL & !RDN & !RESET;

" Logic analyzer trigger
!TRIGGER       = !CSN2 & LATRIG;                  " Negative trig pulse

"------------------------------------------------------------------------------"
" E-Bus acknowledge gathering and generation
"------------------------------------------------------------------------------"
!EACKN         =  LCD & CDD
               #  KEYPAD & CDD
               #  TKNVRAM & CDD
               #  BRDCTRL & CDD
               # !CSN2 & LINK1394 & !I1394_EACKN
               # !CSN2 & ATA & ATA_IORDY
               # !CSN2 & ETHERNET & (!SONIC_DSACK0 # !SONIC_DSACK1)
               # !CSN5 & !CIACKN;


"******************************************************************************"
" IEEE1394 Link signals
"******************************************************************************"
I1394_ERR     :=  LNKDIS &  LNKOT & !LNKEX &  AUTOFEED &  BDBUSY
               #  LNKDIS &  LNKOT &  LNKEX &  AUTOFEED &  I1394_XRDY
               #  LNKDIS &  I1394_ERR;
I1394_ERR.CLK  =  DIVCLK;

"------------------------------------------------------------------------------"
" CLOCKS (HI: LNKDIS = ENABLE, LNKEX = EXT, LNKOT = OUT)
"------------------------------------------------------------------------------"
" STROBEN      : SC2000 CLOCK                                  (I/O)
"              : 118 DATA DIRECTION (HI = TO)                  (INP)
" SELECTIN     : SC2000 DATA DIRECTION (HI = TO)               (INP)
" BDCLK        : BDICLK AND BDOCLK                             (OUT)
" I1394_CLK    : INPUT AND OUTPUT CLOCK                        (OUT)

STROBEN        = !LNKDIS &  PTR_STBN              " 1284
               #  LNKDIS & !LNKOT & DIVCLK;       " SC2000 CLK
STROBEN.OE     = !LNKDIS;

SELECTIN       = !LNKDIS &  PTR_SELN              " 1284
               #  LNKDIS & !LNKEX & !LNKOT;       " SC2000 DIR
SELECTIN.OE    = !LNKDIS #  LNKDIS & !LNKEX;

BDCLK          =  LNKDIS & !LNKEX & !LNKOT & DIVCLK
               #  LNKDIS & !LNKEX &  LNKOT & STROBEN;

I1394_CLK      =  LNKDIS &  LNKEX & !LNKOT & DIVCLK
               #  LNKDIS &  LNKEX &  LNKOT & STROBEN;

"------------------------------------------------------------------------------"
" DATA VALID (HI: LNKDIS = ENABLE, LNKEX = EXT, LNKOT = OUT)
"------------------------------------------------------------------------------"
" AUTOFEED     : DATA VALID                                    (I/O)
" BDOEN        : R/WN CONTROL TO CHIP                          (OUT)
" BDIEN        : DATA VALID (ENABLE) (HI)                      (OUT)
" BDOAVAIL     : DATA AVAILABLE FOR READ (HI)                  (INP)
" BDBUSY       : DO NOT WRITE (HI)                             (INP)
" I1394_RDN    : READ (INPUT) ENABLE (LO)                      (OUT)
" I1394_WRN    : WRITE (OUTPUT) ENABLE (LO)                    (OUT)
" I1394_XRDY   : READY TO RECEIVE DATA (LO)                    (INP)
" I1394_DAVA   : DATA AVAILABLE FOR INPUT (LO)                 (INP)

AUTOFEED       = !LNKDIS &  PTR_AUFD              " 1284
               #  LNKDIS & !LNKEX & !LNKOT &  BDOAVAIL
               #  LNKDIS &  LNKEX & !LNKOT & !I1394_DAVA;
AUTOFEED.OE    = !LNKDIS #  LNKDIS & !LNKOT;

BDOEN          = !LNKDIS #  LNKEX                 " DISABLE TO READ
               #  LNKDIS & !LNKEX & !LNKOT;       " R/WN

BDIEN          =  LNKDIS & !LNKEX &  LNKOT & !BDBUSY &  AUTOFEED
               #  LNKDIS & !LNKEX & !LNKOT &  BDOAVAIL;

I1394_RDN      = !LNKDIS # !LNKEX                 " DISABLE
               # !(LNKDIS &  LNKEX & !LNKOT & !I1394_DAVA);

I1394_WRN      = !LNKDIS # !LNKEX                 " DISABLE
               # !(LNKDIS &  LNKEX &  LNKOT & !I1394_XRDY &  AUTOFEED);

"------------------------------------------------------------------------------"
" SYNC (HI: LNKDIS = ENABLE, LNKEX = EXT, LNKOT = OUT)
"------------------------------------------------------------------------------"
" INITN        : SC2000 SYNC                                   (I/O)
" BDIF2        : SYNC (FIRST BYTE OF A CELL)                   (I/O)
" I1394_SYNC   : FIRST BYTE OF A CELL                          (I/O)

"INITN         =  PTR_INTN;             1284
INITN          = !LNKDIS &  PTR_INTN              " 1284
               #  LNKDIS & !LNKOT & !LNKEX &  BDIF2
               #  LNKDIS & !LNKOT & LNKEX &  I1394_SYNC;
INITN.OE       = !LNKDIS #  LNKDIS & !LNKOT;

BDIF2          =  LNKDIS & !LNKEX &  LNKOT & INITN;
BDIF2.OE       =  LNKDIS & !LNKEX &  LNKOT;

I1394_SYNC     =  LNKDIS &  LNKEX &  LNKOT & INITN;
I1394_SYNC.OE  =  LNKDIS &  LNKEX &  LNKOT;

" DATA_DIR     : LOCK PTR_DDIR HI IN 1394 MODE                 (OUT)

PTR_DDIR       = !LNKDIS &  DATA_DIR              " 1284
               #  LNKDIS;                         " 1394


"******************************************************************************"
" Ethernet - External bus master signals
"******************************************************************************"

"------------------------------------------------------------------------------"
" XBREQn - External Bus Request to SC2000
" - Assert LOW during bus request and bus acknowledge
"------------------------------------------------------------------------------"
XBREQN         =  (SONIC_BRN & SONIC_BGACKN) # ETHRDIS;
CSN3           =  XBREQN;

"------------------------------------------------------------------------------"
" XBGRANTn - External Bus Grant from SC2000
" - Pass this active LOW signal to SONIC
"------------------------------------------------------------------------------"
SONIC_BGN      =  (CSN4 & XBGRANTN) # ETHRDIS;

"------------------------------------------------------------------------------"
" XREQn - External Bus Cycle Request to SC2000
" - Assert LOW during the entire SONIC bus cycle (states 1 thru 7)
" - Enable output while XBGRANTn signal is LOW
"------------------------------------------------------------------------------"
ADDR7          = !(ST1 # ST2 # ST3 # ST4 # ST5 # ST6 # ST7);
ADDR7.OE       = !CSN4;

"------------------------------------------------------------------------------"
" XADDVAL - Address Valid signal to SC2000
" - Asserted HIGH during the address phase of the external master bus cycle
"   (states 1 thru 5)
" - Enable output while XBGRANTn signal is LOW
"------------------------------------------------------------------------------"
ADDR6          =  ST1 # ST2 # ST3 # ST4 # ST5;
ADDR6.OE       = !CSN4;

"------------------------------------------------------------------------------"
" BEn[3:0] - Byte Lane Enable signals to SC2000
" - This bus is asserted LOW to enable 32-bit transactions for the
"   external bus master cycles.
" - Enable output while XBGRANTn signal is LOW
"------------------------------------------------------------------------------"
BEN            =  LOW;
BEN.OE         = !CSN4;

"------------------------------------------------------------------------------"
"  Address/Data Mux Enable and Select
"  - The SONIC has a demuxed address/data bus, but the SC2000 requires
"    the external bus cycle to use a multiplexed address/data bus.
"    The ADMUX_EN and ADMUX_SEL outputs control the external 2:1 mux
"------------------------------------------------------------------------------"
ADMUX_EN       =  LOW;
ADMUX_SEL      =  ST1 # ST2 # ST3 # ST4 # ST5;

"------------------------------------------------------------------------------"
"  SONIC_DSACK 0/1 - Data acknowledge to SONIC
"  - Gate the XEACKN signal with XREQN high.  This effectively delays the
"    SONIC bus cycle, and allows the XEACKN signal to deassert in time for
"    the next SONIC bus master cycle.
"------------------------------------------------------------------------------"
SONIC_DSACK0     =  ADDR5 # !ADDR7;
SONIC_DSACK0.OE  = !SONIC_BGACKN;
SONIC_DSACK1     =  ADDR5 # !ADDR7;
SONIC_DSACK1.OE  = !SONIC_BGACKN;

"------------------------------------------------------------------------------"
" STERMN - Deassert STERMN high at all times.  The assertion of DSACK[1:0]
"          will terminate the SONIC bus master cycle.
"------------------------------------------------------------------------------"
SONIC_STERMN   =  HIGH;

"------------------------------------------------------------------------------"
"  SONIC State Machine runs at 54 MHz
"------------------------------------------------------------------------------"
DMA.CLK        =  CPUCLK;                         " 54 MHz
DMA.AR         =  RESET # ETHRDIS;

"******************************************************************************"
" Ethernet - External bus master state machine
"******************************************************************************"

STATE_DIAGRAM DMA
"------------------------------------------------------------------------------"
"   State 0 - Bus inactive.  Wait for XBGRANTN, SONIC_ECSN and SONIC_BGACKN 
"             to be asserted to start a new bus cycle.
"------------------------------------------------------------------------------"
    STATE STX0:
        IF !CSN4 & !SONIC_BGACKN & !SONIC_ECSN
        THEN STX1
        ELSE STX0;

"------------------------------------------------------------------------------"
"   State 1-5 - Address Phase.  The address phase is generated for five
"               54 MHz clock periods, as required by the SC2000.
"               The following signals are asserted during this phase:
"               ADDVAL, XAD[0] (Read/Write) and ADMUX_SEL. XREQn is also
"               asserted and remains asserted thru state 7.
"------------------------------------------------------------------------------"
    STATE STX1:
        GOTO STX2;

    STATE STX2:
        GOTO STX3;

    STATE STX3:
        GOTO STX4;

    STATE STX4:
        GOTO STX5;

    STATE STX5:
        GOTO STX6;

"------------------------------------------------------------------------------"
"   State 6 - Data Phase.  Deassert ADMUX_SEL, ADDVAL.  Wait for
"             XEACKn or XBERRORn to be asserted by the SC2000.
"------------------------------------------------------------------------------"
    STATE STX6:
        IF !ADDR4 # !ADDR5
        THEN STX7
        ELSE STX6;

"------------------------------------------------------------------------------"
"   State 7 - Data Phase.  Delay one clock.
"------------------------------------------------------------------------------"
    STATE STX7:
        GOTO STX8;

"------------------------------------------------------------------------------"
"   State 8 - Termination Phase.  Deassert XREQn and then wait for 
"             XEACKn and XBERRORn to deassert.  At this point, the
"             SONIC_ASN signal will have deasserted, and the SONIC
"             will be ready for the next cycle.  Go to state 0 to
"             begin the next bus master cycle.
"------------------------------------------------------------------------------"
    STATE STX8:
        IF ADDR4 & ADDR5
        THEN STX0
        ELSE STX8;

end