sdp2005.abl.txt

LSI2005开发板及芯片资料。主芯片为sc2005

    VERSION        node istype 'com';             " Version register
    SWRESET        node istype 'com';             " SW reset register
    CTRL           node istype 'com';             " Control register
    FPCTRL         node istype 'com';             " FP Control register
    INTMASK        node istype 'com';             " Interrupt Mask register
    STATUS1        node istype 'com';             " Status register 1
    STATUS2        node istype 'com';             " Status register 2
    STATUS3        node istype 'com';             " Status register 3
    LATRIG         node istype 'com';             " Logic analyzer trigger

" Software reset register
    ETHRDIS        node istype 'reg';             " Ethernet enable
    LNKDIS         node istype 'reg';             " IEEE1394 enable
    STATEN         node istype 'reg';             " Status bits enable

    SWRSTD = [ 0, 0, 0, 0, 0, ETHRDIS, LNKDIS, STATEN ];
    SWRSTR = [ ETHRDIS, LNKDIS, STATEN ];

" Control register
    XPTSEL         node istype 'reg';             " NIM / MPEG Streamer Select
    AUXPAR         node istype 'reg';             " Aux port / IEEE1284 select
    LNKEX          node istype 'reg';             " IEEE1394 select
    LNKOT          node istype 'reg';             " IEEE1394 direction

    CTRLD = [ 0, 0, 0, 0, XPTSEL, AUXPAR, LNKEX, LNKOT ]; "modified for SDP2005
    CTRLR = [ XPTSEL, AUXPAR, LNKEX, LNKOT ];

" Front Panel Control register
    CPUALIVE       node istype 'reg';             " Front Panel LED
    KPDWR1         node istype 'reg';             " Keypad write 1
    KPDWR0         node istype 'reg';             " Keypad write 0

    FPCTRLD = [ 0, 0, 0, 0, 0, CPUALIVE, KPDWR1, KPDWR0 ]; 
    FPCTRLR = [ CPUALIVE, KPDWR1, KPDWR0 ];

" Interrupt Mask  register
    ATAINTMSK     node istype 'reg';             " Mask ATA interrupt
    I1394MSK      node istype 'reg';             " Mask 1394 interrupt

    INTMASKD = [ 0, 0, 0, 0, 0, 0, I1394MSK, ATAINTMSK ]; 
    INTMASKR = [ I1394MSK, ATAINTMSK ];

" Status register 1
    COMPV_SEL      pin;                           " Component video select
    GPJ1           pin;                           " General purpose jumper 1
    GPJ0           pin;                           " General purpose jumper 0
    CH_LOCK        pin;                           " NIM lock signal
"    FP_INTB        pin;                            Front panel interrupt

"    STAT1D = [ 0, 0, COMPV_SEL, GPJ1, GPJ0, 0, CH_LOCK, FP_INTB ];
    STAT1D = [ 0, 0, COMPV_SEL, GPJ1, GPJ0, 0, CH_LOCK, 0 ]; "no FP_INTB

" Status register 2
    I1394_ERR      node istype 'reg';             " Error signal
    I1394_DAVA     pin;                           " Data available
    I1394_XRDY     pin;                           " Ready to receive
    I1394_INTB     pin;                           " Interrupt

    STAT2D = [ 0, 0, 0, 0, I1394_ERR, I1394_DAVA, I1394_XRDY, I1394_INTB ];
    STAT2R = [ I1394_ERR ];

" Status register 3
    ATA_CBLIDN     pin;                           " ATA Cable identifier 
    ATA_DASPN      pin;                           " ATA Device Active

    STAT3D = [ 0, 0, 0, 0, 0, 0, ATA_CBLIDN, ATA_DASPN ];

" Logic analyzer trigger
    TRIGGER        pin istype 'com';              " Logic analyzer trigger

"------------------------------------------------------------------------------"
" On-board IEEE1394 Link
"------------------------------------------------------------------------------"
    BDCLK          pin istype 'com';              " BDI/BDO MPEG i/f clock
    BDOEN          pin istype 'com';              " BDO bus enable
    BDIEN          pin istype 'com';              " BDI bus enable
    BDIF2          pin istype 'com';              " BDI sync
    BDBUSY         pin;                           " BDI busy
    BDOAVAIL       pin;                           " BDO data available

"------------------------------------------------------------------------------"
" External IEEE1394 interface
"------------------------------------------------------------------------------"
    I1394_CLK      pin istype 'com';              " Clock
    I1394_RDN      pin istype 'com';              " Read signal
    I1394_WRN      pin istype 'com';              " Write signal
    I1394_SYNC     pin istype 'com';              " Sync

"------------------------------------------------------------------------------"
" IEEE1284 interface
"------------------------------------------------------------------------------"
    PTR_STBN       pin;                           " Data strobe
    PTR_INTN       pin;                           " Reset
    PTR_SELN       pin;                           " Select in
    PTR_AUFD       pin;                           " Autofeed
    PTR_DDIR       pin istype 'com';              " Data direction

"------------------------------------------------------------------------------"
" SONIC Ethernet controller and state machine
"------------------------------------------------------------------------------"
    SONIC_BRN      pin;                           " Bus request
    SONIC_BGN      pin istype 'com';              " Bus granted
    SONIC_BGACKN   pin;                           " Bus granted ack.
    SONIC_ECSN     pin;                           " Chip-select
    SONIC_ASN      pin;                           " Address strobe
    SONIC_STERMN   pin istype 'com';              " Sync termination
    BREQOE         node istype 'com';             " Bus request enable

    ADMUX_EN       pin istype 'com';              " Addr/data MUX enable
    ADMUX_SEL      pin istype 'com';              " Addr/data MUX select

    DMA_ST0        pin istype 'reg';              " State-machine bit 0
    DMA_ST1        pin istype 'reg';              " State-machine bit 0
    DMA_ST2        pin istype 'reg';              " State-machine bit 0
    DMA_ST3        pin istype 'reg';              " State-machine bit 0

    DMA = [DMA_ST3..DMA_ST0];

    ST0  = DMA == ^d0;
    ST1  = DMA == ^d1;
    ST2  = DMA == ^d2;
    ST3  = DMA == ^d3;
    ST4  = DMA == ^d4;
    ST5  = DMA == ^d5;
    ST6  = DMA == ^d6;
    ST7  = DMA == ^d7;
    ST8  = DMA == ^d8;
    ST9  = DMA == ^d9;
    ST10 = DMA == ^d10;

    STX0  = ^d0;
    STX1  = ^d1;
    STX2  = ^d2;
    STX3  = ^d3;
    STX4  = ^d4;
    STX5  = ^d5;
    STX6  = ^d6;
    STX7  = ^d7;
    STX8  = ^d8;
    STX9  = ^d9;
    STX10 = ^d10;

"------------------------------------------------------------------------------"
" External Interface signals added/modified for SDP2005
"------------------------------------------------------------------------------"
    XPT_SEL        pin istype 'com';              " NIM / MPEG Streamer Select
    CPU_ALIVE      pin istype 'com';              " Front Panel LED
    KPD_WR1        pin istype 'com';              " Keypad write 1
    KPD_WR0        pin istype 'com';              " Keypad write 0
    
"------------------------------------------------------------------------------"
" Unused pins
"------------------------------------------------------------------------------"
    BUSY           pin;
    CSN5           pin;
    FAULTN         pin;
    SELECT         pin;
    SONIC_DSN      pin;
    SONIC_MRW      pin;


"******************************************************************************"
EQUATIONS 
"******************************************************************************"

"------------------------------------------------------------------------------"
" Clock
"------------------------------------------------------------------------------"
DIVCLK        := !DIVCLK;                         " Divide by 2 (13.5 MHz)
DIVCLK.CLK     =  MAINCLK;

"------------------------------------------------------------------------------"
" Internal signals for modified E-Bus timing
"------------------------------------------------------------------------------"
CSD           := !CSN2 & (!RDN # !WRN);           " 1 clock delayed access
CDD           :=  CSD;                            " 2 clock delayed access
CSX            =  CSD & (!RDN # !WRN);            " Late access
WDN           := !CSN2 & !WRN;                    " 1 clock delayed write
WTS            =  (!CSN2 & !WRN) # WDN;           " Extended write
RCK           :=  WTS & !CSD;                     " Register write clock

TIMING.CLK     =  CPUCLK;
TIMING.AR      =  RESET;


"             I/O Timing  (CPUCLK = 54 MHz, 18.5 ns)
"            ----------------------------------------
"
" CPUCLK    __|--|__|--|__|--|__|--|__|--| / __|--|__|--|__|--|__|--
"
" CSN2      --------|_____________________ / ___________|-----------
"
" RDN, WRN  --------------|_______________ / ________|--------------
"
" CSD       ____________________|--------- / --------------|________
"
" CDD       __________________________|--- / --------------------|__
"
" CSX       ____________________|--------- / --------|______________
"
" WDN       ____________________|--------- / --------------|________
"
" WTS       ______________|--------------- / --------------|________
"
" RCK       ____________________|-----|___ / _______________________


"------------------------------------------------------------------------------"
" Chip-select 2 address decoding
"------------------------------------------------------------------------------"
"   E-Bus address lines are latched internally on the falling edge of CSD.
"   This prevents the address bus contention (caused by SONIC) from affecting
"   the address decode in the PLD.
L_ADDRESS_MSB     := ADDRESS_MSB;
L_ADDRESS_MSB.CLK  = CPUCLK & !CSD;

LINK1394       =  L_ADDRESS_MSB == ^h60;
ETHERNET       =  L_ADDRESS_MSB == ^h62;
LCD            =  L_ADDRESS_MSB == ^h64;
KEYPAD         =  L_ADDRESS_MSB == ^h66;
TKNVRAM        =  L_ADDRESS_MSB == ^h68;
BRDCTRL        =  L_ADDRESS_MSB == ^h70;
ATA	         =  L_ADDRESS_MSB == ^h72;          " Added for ATA interface
	
VERSION        =  BRDCTRL & (ADDRESS_LSB == ^h00);
SWRESET        =  BRDCTRL & (ADDRESS_LSB == ^h02);
CTRL           =  BRDCTRL & (ADDRESS_LSB == ^h10);
FPCTRL         =  BRDCTRL & (ADDRESS_LSB == ^h12);
INTMASK        =  BRDCTRL & (ADDRESS_LSB == ^h14);
STATUS1        =  BRDCTRL & (ADDRESS_LSB == ^h20);
STATUS2        =  BRDCTRL & (ADDRESS_LSB == ^h22);
STATUS3        =  BRDCTRL & (ADDRESS_LSB == ^h24);
LATRIG         =  BRDCTRL & (ADDRESS_LSB == ^h30);

ATACSN0        =  ATA & (!ADDR5);                 " Added for ATA interface
ATACSN1        =  ATA & (!ADDR6);

"------------------------------------------------------------------------------"
" Internal IEEE1394 E-Bus signals
"------------------------------------------------------------------------------"
I1394_CSN      = !(LINK1394 &  CSX);              " 130 nS TO DTACK
I1394_RWN      = !(LINK1394 &  WTS);              " R/W signal

FWINT          =  LOW;
FWINT.OE       =  LNKDIS & !LNKEX & !I1394_INTB & I1394MSK  " On-board 1394 interrupt
               #  LNKDIS &  LNKEX & !I1394_XRDY & I1394MSK  " External 1394 ready
               #  LNKDIS &  LNKEX & !I1394_DAVA & I1394MSK  " External 1394 data available
               #  LNKDIS &  I1394_ERR & I1394MSK            " 1394 Link error
               #  ATA_INTRQ &  ATAINTMSK;                   " 1394 Link error

"------------------------------------------------------------------------------"
" SONIC Ethernet controller E-Bus signals
"------------------------------------------------------------------------------"
SONIC_CLK      =  DIVCLK;                         " SONIC clock
SONIC_SASN     = !(ETHERNET & CSD);               " SONIC address strobe
SONIC_SRW      = !(!CSN2 & ETHERNET & !WRN);      " SONIC read/write

SONIC_CSN     :=  SONIC_SASN;                     " SONIC chip select
SONIC_CSN.CLK  =  DIVCLK;

ETHINT         =  LOW;
ETHINT.OE      = !SONIC_INTB;

"------------------------------------------------------------------------------"
" Front panel E-Bus signals
"------------------------------------------------------------------------------"
FP_CSN         = !(LCD & (CDD # !CSN2));          " 245 BUFFER EN
FP_DSN         = !(LCD &  CSX &  CDD);            " E CLOCK 
FP_WRN         = !(LCD &  WTS);                   " REALLY LCD_WRN

KPD_CSN        = !(KEYPAD &  CSX & !WTS);         " 244 ENABLE (READ ONLY)

"------------------------------------------------------------------------------"
" Real-time clock E-Bus signals
"------------------------------------------------------------------------------"
RTC_CSN        = !(TKNVRAM & !CSN2);              " 120 ns access time
RTC_WRN        =  WRN;                            " OE = RDN

"------------------------------------------------------------------------------"
" ATA Interface signals
"------------------------------------------------------------------------------"
PLD_ATA_CSN0   = !(ATACSN0 & !CSN2);              " Chipselect 0
PLD_ATA_CSN1   = !(ATACSN1 & !CSN2);              " Chipselect 1
BUF_OEN        = !(ATA  & !CSN2 );          " OE for Buffers on ATA boad

"------------------------------------------------------------------------------"
" External Signals added for SDP2005
"------------------------------------------------------------------------------"
XPT_SEL        =  XPTSEL;
CPU_ALIVE      =  CPUALIVE;
KPD_WR1        =  KPDWR1;
KPD_WR0        =  KPDWR0;