sdp2005.abl.txt

LSI2005开发板及芯片资料。主芯片为sc2005

"******************************************************************************"
"
"   SDP2000/SDP2005 Main Board Rev. A
"
"   PLD Code, Version 2.1
"
"******************************************************************************"
"
"   Revision history
"       v1.0   First formal SDP2000 release
"       v2.0   First formal SDP2005 release
"       v2.1   Fixed functionality of IEEE1284 interface
"
"   Target: Xilinx XC95144XL-10-TQ144
"
"******************************************************************************"
Module sdp2000a;
Title 'PLD for SDP2000 Main Board';


"******************************************************************************"
" Pin Information
"******************************************************************************"
"
" Signal Name   |   Pin #     |  Pin Type  |   From / To
" ------------- | ----------- | ---------- | -------------
" AD0           |   Pin 52    |   In/Out   |   System Addr/Data bus
" AD1           |   Pin 106   |   In/Out   |   System Addr/Data bus
" AD2           |   Pin 110   |   In/Out   |   System Addr/Data bus
" AD3           |   Pin 113   |   In/Out   |   System Addr/Data bus
" AD4           |   Pin 119   |   In/Out   |   System Addr/Data bus
" AD5           |   Pin 53    |   In/Out   |   System Addr/Data bus
" AD6           |   Pin 69    |   In/Out   |   System Addr/Data bus
" AD7           |   Pin 23    |   In/Out   |   System Addr/Data bus
" AD24          |   Pin 128   |   In       |   System Addr/Data bus
" AD25          |   Pin 125   |   In       |   System Addr/Data bus
" AD26          |   Pin 130   |   In       |   System Addr/Data bus
" AD27          |   Pin 121   |   In       |   System Addr/Data bus
" AD28          |   Pin 134   |   In       |   System Addr/Data bus
" AD29          |   Pin 118   |   In       |   System Addr/Data bus
" AD30          |   Pin 117   |   In       |   System Addr/Data bus
" AD31          |   Pin 135   |   In       |   System Addr/Data bus
" ADDR0         |   Pin 38    |   In       |   System Address bus
" ADDR1         |   Pin 6     |   In       |   System Address bus
" ADDR2         |   Pin 5     |   In       |   System Address bus
" ADDR3         |   Pin 3     |   In       |   System Address bus
" ADDR4         |   Pin 79    |   In       |   System Address + bus master
" ADDR5         |   Pin 77    |   In       |   System Address + bus master
" ADDR6         |   Pin 142   |   In/Out   |   System Address + bus master
" ADDR7         |   Pin 4     |   In/Out   |   System Address + bus master
" ADMUX_EN      |   Pin 104   |   Out      |   to Ethernet controller bus MUX
" ADMUX_SEL     |   Pin 74    |   Out      |   to Ethernet controller bus MUX
" AUTOFEED      |   Pin 91    |   In/Out   |   Aux Port + to SC2000 IEEE1284
" BDBUSY        |   Pin 14    |   In       |   from IEEE1394 Link
" BDCLK         |   Pin 51    |   Out      |   to IEEE1394 Link
" BDIEN         |   Pin 103   |   Out      |   to IEEE1394 Link
" BDIF2         |   Pin 34    |   In/Out   |   from/to IEEE1394 Link
" BDOAVAIL      |   Pin 94    |   In       |   from IEEE1394 Link
" BDOEN         |   Pin 49    |   Out      |   to IEEE1394 Link
" BEN0          |   Pin 129   |   Out      |   to SC2000 E-Bus
" BEN1          |   Pin 131   |   Out      |   to SC2000 E-Bus
" BEN2          |   Pin 56    |   Out      |   to SC2000 E-Bus
" BEN3          |   Pin 68    |   Out      |   to SC2000 E-Bus
" BUSY          |   Pin 96    |     --     |   
" CH_LOCK       |   Pin 111   |   In       |   from NIM
" CIACKN        |   Pin 76    |   In       |   from CI controller
" COMPV_SEL     |   Pin 107   |   In       |   from jumper
" CPUCLK        |   Pin 30    |   In       |   from SC2000 clock i/f
" CSN2          |   Pin 116   |   In       |   from SC2000 E-Bus
" CSN3          |   Pin 132   |   Out      |   to SC2000 slave
" CSN4          |   Pin 2     |   In       |   from SC2000 slave
" CSN5          |   Pin 11    |     --     |   
" DATA_DIR      |   Pin 15    |   In       |   from SC2000 IEEE1284
" BUF_OEN       |   Pin 137   |   Out      |   to ATA i/f buffers
" XPT_SEL       |   Pin 71    |   Out      |   to NIM / MPEG Streamer Select
" PLD_ATA_CSN1  |   Pin 80    |   Out      |   to ATA interface
" PLD_ATA_CSN0  |   Pin 7     |   Out      |   to ATA interface
" ATA_INTRQ     |   Pin 78    |   In       |   Interrupt from ATA Interface
" EACKN         |   Pin 82    |   Out      |   to SC2000 E-Bus
" ETHINT        |   Pin 60    |   Out      |   to SC2000 interrupts
" FAULTN        |   Pin 43    |     --     |   
" FP_CSN        |   Pin 17    |   Out      |   to front panel
" FP_DSN        |   Pin 19    |   Out      |   to front panel
" ATA_IORDY     |   Pin 25    |   In       |   from ATA Interface
" FP_WRN        |   Pin 21    |   Out      |   to front panel
" FWINT         |   Pin 87    |   Out      |   to SC2000 interrupts
" GPJ0          |   Pin 27    |   In       |   from jumper
" GPJ1          |   Pin 102   |   In       |   from jumper
" I1394_CLK     |   Pin 46    |   Out      |   to external IEEE1394
" I1394_CSN     |   Pin 31    |   Out      |   to IEEE1394 Link
" ATA_CBLIDN    |   Pin 101   |   In       |   status from ATA interface
" I1394_EACKN   |   Pin 115   |   In       |   from IEEE1394 Link
" I1394_INTB    |   Pin 16    |   In       |   from IEEE1394 Link
" KPD_WR0       |   Pin 50    |   Out      |   to Front Panel keypad
" I1394_RWN     |   Pin 26    |   Out      |   to IEEE1394 Link
" CPU_ALIVE     |   Pin 48    |   Out      |   to Front Panel LED
" KPD_WR1       |   Pin 44    |   Out      |   to Front Panel keypad
" ATA_DASPN     |   Pin 100   |   In       |   Status from ATA Interface
" INITN         |   Pin 92    |   In/Out   |   Aux Port + to SC2000 IEEE1284
" KPD_CSN       |   Pin 28    |   Out      |   to front panel
" MAINCLK       |   Pin 32    |   In       |   from system clock
" MODEM_CSN     |   Pin 81    |   Out      |   to modem
" PTR_AUFD      |   Pin 20    |   In       |   from IEEE1284 interface
" PTR_DDIR      |   Pin 105   |   Out      |   to IEEE1284 interface
" PTR_INTN      |   Pin 86    |   In       |   from IEEE1284 interface
" PTR_SELN      |   Pin 22    |   In       |   from IEEE1284 interface
" PTR_STBN      |   Pin 85    |   In       |   from IEEE1284 interface
" RDN           |   Pin 139   |   In       |   from SC2000 E-Bus
" RESET         |   Pin 143   |   In       |   from system reset
" RTC_CSN       |   Pin 12    |   Out      |   to timekeeping NVRAM
" RTC_WRN       |   Pin 133   |   Out      |   to timekeeping NVRAM
" SELECT        |   Pin 83    |     --     |   
" SELECTIN      |   Pin 98    |   Out      |   to SC2000 Aux Port or IEEE1284
" SFACK         |   Pin 75    |   In       |   from Sync. FLASH
" SONIC_ASN     |   Pin 33    |   In       |   from Ethernet controller
" SONIC_BGACKN  |   Pin 70    |   In       |   from Ethernet controller
" SONIC_BGN     |   Pin 61    |   Out      |   to Ethernet controller
" SONIC_BRN     |   Pin 136   |   In       |   from Ethernet controller
" SONIC_CLK     |   Pin 138   |   Out      |   to Ethernet controller
" SONIC_CSN     |   Pin 35    |   Out      |   to Ethernet controller
" SONIC_DSACK0  |   Pin 126   |   In/Out   |   to/form Ethernet controller
" SONIC_DSACK1  |   Pin 140   |   In/Out   |   to/form Ethernet controller
" SONIC_DSN     |   Pin 97    |     --     |   
" SONIC_ECSN    |   Pin 39    |   In       |   from Ethernet controller
" SONIC_INTB    |   Pin 24    |   In       |   from Ethernet controller
" SONIC_MRW     |   Pin 95    |     --     |   
" SONIC_SASN    |   Pin 124   |   Out      |   to Ethernet controller
" SONIC_SRW     |   Pin 9     |   Out      |   to Ethernet controller
" SONIC_STERMN  |   Pin 88    |   Out      |   to Ethernet controller
" STROBEN       |   Pin 93    |   In/Out   |   Aux Port + to SC2000 IEEE1284
" TRIGGER       |   Pin 13    |   Out      |   to logic analyzer
" WRN           |   Pin 112   |   In       |   from SC2000 E-Bus
" XBGRANTN      |   Pin 40    |   In       |   from SC2000 slave
" XBREQN        |   Pin 66    |   Out      |   to SC2000 slave


"******************************************************************************"
DECLARATIONS
"******************************************************************************"

PLD_VER = [0,0,1,0,0,0,0,1];                      " PLD code version 2.1
"PLD_VER = ^h21;

LOW  = 0;
HIGH = 1;

"------------------------------------------------------------------------------"
" Clocks
"------------------------------------------------------------------------------"
    CPUCLK         pin;                           " 54 MHz
    MAINCLK        pin;                           " 27 MHz
    DIVCLK         node istype 'reg';             " pin is used elsewhere

"------------------------------------------------------------------------------"
" E-Bus
"------------------------------------------------------------------------------"
    RESET          pin;                           " System reset
    RDN            pin;                           " E-Bus read
    WRN            pin;                           " E-Bus write
    EACKN          pin istype 'com';              " Acknowledge out
    SFACK          pin;                           " Sync FLASH ack in
    CIACKN         pin;                           " Common interface ack in
    FWINT          pin istype 'com';              " IEEE1394 / ATA interrupt
    ETHINT         pin istype 'com';              " Ethernet interrupt

"------------------------------------------------------------------------------"
" Modified E-Bus timing
"------------------------------------------------------------------------------"
    CSD            node istype 'reg';             " 1 clock delayed access
    CDD            node istype 'reg';             " 2 clock delayed access
    CSX            node istype 'com';             " Late access
    WDN            node istype 'reg';             " 1 clock delayed write
    WTS            node istype 'com';             " Extended write
    RCK            node istype 'reg';             " CTRL register clock
    
    TIMING = [CSD, CDD, WDN, RCK];

"------------------------------------------------------------------------------"
" External bus master pins
"------------------------------------------------------------------------------"
    XBREQN         pin istype 'com';              " External bus request
    XBGRANTN       pin;                           " External bus granted
    CSN3           pin istype 'com';              " Alternate XBREQn
    CSN4           pin;                           " Alternate XBGRANTn

    ADDR7          pin istype 'com';              " XREQn (I/O)
    ADDR6          pin istype 'com';              " XADDVAL (I/O)
    ADDR5          pin;                           " XEACKn (input)
    ADDR4          pin;                           " XBERRORn (input)

    BEN3           pin istype 'com';              " Byte enable 3
    BEN2           pin istype 'com';              " Byte enable 2
    BEN1           pin istype 'com';              " Byte enable 1
    BEN0           pin istype 'com';              " Byte enable 0

    BEN = [BEN3..BEN0];

"------------------------------------------------------------------------------"
" Aux port / IEEE1284 signals
"------------------------------------------------------------------------------"
    STROBEN        pin istype 'com';              " Aux clock / 1284 strobe
    INITN          pin istype 'com';              " Aux sync / 1284 reset
    SELECTIN       pin istype 'com';              " Aux dir. / 1284 select
    AUTOFEED       pin istype 'com';              " Aux valid / Autofeed
    DATA_DIR       pin;                           " 1284 Data direction

"------------------------------------------------------------------------------"
" Chip-select 2 address decoding
"------------------------------------------------------------------------------"
    CSN2           pin;                           " Chip-select 2

    AD31           pin;                           " Address bit 23
    AD30           pin;                           " Address bit 22
    AD29           pin;                           " Address bit 21
    AD28           pin;                           " Address bit 20
    AD27           pin;                           " Address bit 19
    AD26           pin;                           " Address bit 18
    AD25           pin;                           " Address bit 17
    AD24           pin;                           " Address bit 16

    ADDRESS_MSB = [AD31..AD24];
    
    LAD31..LAD24   node istype 'reg';
    
    L_ADDRESS_MSB = [LAD31..LAD24];               " Latched Address bits 23-16

    LINK1394       node istype 'com';             " IEEE1394 Link
    ETHERNET       node istype 'com';             " Ethernet controller
    LCD            node istype 'com';             " Front panel LCD
    KEYPAD         node istype 'com';             " Front panel keypad
    TKNVRAM        node istype 'com';             " Timekeeping NVRAM
    MODEM          node istype 'com';             " Modem board
    BRDCTRL        node istype 'com';             " Control registers

"------------------------------------------------------------------------------"
" Peripherals on chip-select 2
"------------------------------------------------------------------------------"
" IEEE1394 Link
    I1394_CSN      pin istype 'com';              " Chip-select
    I1394_RWN      pin istype 'com';              " Read/Write signal
    I1394_EACKN    pin;                           " Acknowledge

" Ethernet controller
    SONIC_CLK      pin istype 'com';              " Clock
    SONIC_CSN      pin istype 'reg';              " Chip-select
    SONIC_SASN     pin istype 'com';              " Address strobe
    SONIC_SRW      pin istype 'com';              " Read/Write signal
    SONIC_DSACK0   pin istype 'com';              " Acknowledge 0
    SONIC_DSACK1   pin istype 'com';              " Acknowledge 1
    SONIC_INTB     pin;                           " Interrupt

" Front panel
    FP_CSN         pin istype 'com';              " Chip-select
    FP_WRN         pin istype 'com';              " Write signal
    FP_DSN         pin istype 'com';              " Data strobe
    KPD_CSN        pin istype 'com';              " Keypad chip-select

" Real-time clock
    RTC_CSN        pin istype 'com';              " Chip-select
    RTC_WRN        pin istype 'com';              " Write signal

" Modem board
    MODEM_CSN      pin istype 'com';              " Chip-select

" ATA Board
    ATA            node istype 'com';             " ATA Chipselect
    ATACSN0        node istype 'com';             " Internal ATA Chipselect0
    ATACSN1        node istype 'com';             " Internal ATA Chipselect1    
    PLD_ATA_CSN0   pin istype 'com';              " ATA Chipselect0
    PLD_ATA_CSN1   pin istype 'com';              " ATA Chipselect1    
    BUF_OEN        pin istype 'com';              " OE for ATA board buffers
    ATA_IORDY      pin;                           " IORDY from ATA Interface
    ATA_INTRQ      pin;                           " Interrupt from ATA i/f

"------------------------------------------------------------------------------"
" Internal registers
"------------------------------------------------------------------------------"
    ADDR3          pin;                           " Address bit 3
    ADDR2          pin;                           " Address bit 2
    ADDR1          pin;                           " Address bit 1
    ADDR0          pin;                           " Address bit 0

    ADDRESS_LSB = [ADDR7..ADDR0];

    AD7            pin istype 'com';              " Data 7
    AD6            pin istype 'com';              " Data 6
    AD5            pin istype 'com';              " Data 5
    AD4            pin istype 'com';              " Data 4
    AD3            pin istype 'com';              " Data 3
    AD2            pin istype 'com';              " Data 2
    AD1            pin istype 'com';              " Data 1
    AD0            pin istype 'com';              " Data 0

    DATA = [AD7..AD0];