📄 6805.vhd
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x"D7" | x"DF" | x"E7" | x"EF" | -- STA oprx16,X, STX oprx16,X, STA oprx8,X, STX oprx8,X
x"F7" | x"FF" => -- STA ,X, STX ,X
wr <= CPUread;
addrMux <= addrPC;
mainFSM <= "0010";
when x"80" | x"82" => -- RTI, RTT
regX <= datain;
regSP <= regSP + 1;
mainFSM <= "0110";
when x"83" => -- SWI
regSP <= regSP - 1;
dataMux <= outX;
help(7) <= '1';
help(6) <= '1';
help(5) <= '1';
help(4) <= flagH;
help(3) <= flagI;
help(2) <= flagN;
help(1) <= flagZ;
help(0) <= flagC;
mainFSM <= "0110";
when x"A0" | x"B0" | x"C0" | x"D0" | x"E0" | x"F0" => -- SUB #opr8i, SUB opr8a, SUB opr16a, SUB oprx16,X, SUB oprx8,X, SUB ,X
addrMux <= addrPC;
regA <= regA - datain;
tres := regA - datain;
flagN <= tres(7);
if tres = x"00" then
flagZ <= '1';
else
flagZ <= '0';
end if;
flagC <= ((not regA(7)) and datain(7)) or
(datain(7) and tres(7)) or
(tres(7) and (not regA(7)));
if opcode = x"A0" then
regPC <= regPC + 1;
end if;
mainFSM <= "0010";
when x"A1" | x"B1" | x"C1" | x"D1" | x"E1" | x"F1" => -- CMP #opr8i, CMP opr8a, CMP opr16a, CMP oprx16,X, CMP oprx8,X, CMP ,X
addrMux <= addrPC;
tres := regA - datain;
flagN <= tres(7);
if tres = x"00" then
flagZ <= '1';
else
flagZ <= '0';
end if;
flagC <= ((not regA(7)) and datain(7)) or
(datain(7) and tres(7)) or
(tres(7) and (not regA(7)));
if opcode = x"A1" then
regPC <= regPC + 1;
end if;
mainFSM <= "0010";
when x"A2" | x"B2" | x"C2" | x"D2" | x"E2" | x"F2" => -- SBC #opr8i, SBC opr8a, SBC opr16a, SBC oprx16,X, SBC oprx8,X, SBC ,X
addrMux <= addrPC;
regA <= regA - datain - ("0000000" & flagC);
tres := regA - datain - ("0000000" & flagC);
flagN <= tres(7);
if tres = x"00" then
flagZ <= '1';
else
flagZ <= '0';
end if;
flagC <= ((not regA(7)) and datain(7)) or
(datain(7) and tres(7)) or
(tres(7) and (not regA(7)));
if opcode = x"A2" then
regPC <= regPC + 1;
end if;
mainFSM <= "0010";
when x"A3" | x"B3" | x"C3" | x"D3" | x"E3" | x"F3" => -- CPX #opr8i, CPX opr8a, CPX opr16a, CPX oprx16,X, CPX oprx8,X, CPX ,X
addrMux <= addrPC;
tres := regX - datain;
flagN <= tres(7);
if tres = x"00" then
flagZ <= '1';
else
flagZ <= '0';
end if;
flagC <= ((not regX(7)) and datain(7)) or
(datain(7) and tres(7)) or
(tres(7) and (not regX(7)));
if opcode = x"A3" then
regPC <= regPC + 1;
end if;
mainFSM <= "0010";
when x"A4" | x"B4" | x"C4" | x"D4" | x"E4" | x"F4" => -- AND #opr8i, AND opr8a, AND opr16a, AND oprx16,X, AND oprx8,X, AND ,X
addrMux <= addrPC;
regA <= regA and datain;
tres := regA and datain;
flagN <= tres(7);
if tres = x"00" then
flagZ <= '1';
else
flagZ <= '0';
end if;
if opcode = x"A4" then
regPC <= regPC + 1;
end if;
mainFSM <= "0010";
when x"A5" | x"B5" | x"C5" | x"D5" | x"E5" | x"F5" => -- BIT #opr8i, BIT opr8a, BIT opr16a, BIT oprx16,X, BIT oprx8,X, BIT ,X
addrMux <= addrPC;
tres := regA and datain;
flagN <= tres(7);
if tres = x"00" then
flagZ <= '1';
else
flagZ <= '0';
end if;
if opcode = x"A5" then
regPC <= regPC + 1;
end if;
mainFSM <= "0010";
when x"A6" | x"B6" | x"C6" | x"D6" | x"E6" | x"F6" => -- LDA #opr8i, LDA opr8a, LDA opr16a, LDA oprx16,X, LDA oprx8,X, LDA ,X
addrMux <= addrPC;
regA <= datain;
flagN <= datain(7);
if datain = x"00" then
flagZ <= '1';
else
flagZ <= '0';
end if;
if opcode = x"A6" then
regPC <= regPC + 1;
end if;
mainFSM <= "0010";
when x"A8" | x"B8" | x"C8" | x"D8" | x"E8" | x"F8" => -- EOR #opr8i, EOR opr8a, EOR opr16a, EOR oprx16,X, EOR oprx8,X, EOR ,X
addrMux <= addrPC;
regA <= regA xor datain;
tres := regA xor datain;
flagN <= tres(7);
if tres = x"00" then
flagZ <= '1';
else
flagZ <= '0';
end if;
if opcode = x"A8" then
regPC <= regPC + 1;
end if;
mainFSM <= "0010";
when x"A9" | x"B9" | x"C9" | x"D9" | x"E9" | x"F9" => -- ADC #opr8i, ADC opr8a, ADC opr16a, ADC oprx16,X, ADC oprx8,X, ADC ,X
addrMux <= addrPC;
regA <= regA + datain + ("0000000" & flagC);
tres := regA + datain + ("0000000" & flagC);
flagN <= tres(7);
if tres = x"00" then
flagZ <= '1';
else
flagZ <= '0';
end if;
flagH <= (regA(3) and datain(3)) or
(datain(3) and (not tres(3))) or
((not tres(3)) and regA(3));
flagC <= (regA(7) and datain(7)) or
(datain(7) and (not tres(7))) or
((not tres(7)) and regA(7));
if opcode = x"A9" then
regPC <= regPC + 1;
end if;
mainFSM <= "0010";
when x"AA" | x"BA" | x"CA" | x"DA" | x"EA" | x"FA" => -- ORA #opr8i, ORA opr8a, ORA opr16a, ORA oprx16,X, ORA oprx8,X, ORA ,X
addrMux <= addrPC;
regA <= regA or datain;
tres := regA or datain;
flagN <= tres(7);
if tres = x"00" then
flagZ <= '1';
else
flagZ <= '0';
end if;
if opcode = x"AA" then
regPC <= regPC + 1;
end if;
mainFSM <= "0010";
when x"AB" | x"BB" | x"CB" | x"DB" | x"EB" | x"FB" => -- ADD #opr8i, ADD opr8a, ADD opr16a, ADD oprx16,X, ADD oprx8,X, ADD ,X
addrMux <= addrPC;
regA <= regA + datain;
tres := regA + datain;
flagN <= tres(7);
if tres = x"00" then
flagZ <= '1';
else
flagZ <= '0';
end if;
flagH <= (regA(3) and datain(3)) or
(datain(3) and (not tres(3))) or
((not tres(3)) and regA(3));
flagC <= (regA(7) and datain(7)) or
(datain(7) and (not tres(7))) or
((not tres(7)) and regA(7));
if opcode = x"AB" then
regPC <= regPC + 1;
end if;
mainFSM <= "0010";
when x"AE" | x"BE" | x"CE" | x"DE" | x"EE" | x"FE" => -- LDX #opr8i, LDX opr8a, LDX opr16a, LDX oprx16,X, LDX oprx8,X, LDX ,X
addrMux <= addrPC;
regX <= datain;
flagN <= datain(7);
if datain = x"00" then
flagZ <= '1';
else
flagZ <= '0';
end if;
if opcode = x"AE" then
regPC <= regPC + 1;
end if;
mainFSM <= "0010";
when x"AD" => -- BSR rel
wr <= CPUread;
addrMux <= addrPC;
if help(7) = '0' then
regPC <= regPC + (x"00" & help);
else
regPC <= regPC + (x"FF" & help);
end if;
regSP <= regSP - 1;
mainFSM <= "0010";
when x"BD" => -- JSR opr8a
wr <= CPUread;
addrMux <= addrPC;
regPC <= x"00" & help;
regSP <= regSP - 1;
mainFSM <= "0010";
when x"CD" | x"DD" => -- JSR opr16a, JSR oprx16,X
regSP <= regSP - 1;
dataMux <= outPCH;
mainFSM <= "0110";
when x"ED" => -- JSR oprx8,X
wr <= CPUread;
addrMux <= addrPC;
regPC <= (x"00" & help) + (x"00" & regX);
regSP <= regSP - 1;
mainFSM <= "0010";
when x"FD" => -- JSR ,X
wr <= CPUread;
addrMux <= addrPC;
regPC <= (x"00" & regX);
regSP <= regSP - 1;
mainFSM <= "0010";
when others =>
mainFSM <= "0000";
end case; -- opcode
when "0110" => --##################### instruction cycle 5
case opcode is
when x"80" | x"82" => -- RTI, RTT
regPC(15 downto 8) <= datain;
regSP <= regSP + 1;
mainFSM <= "0111";
when x"83" => -- SWI
regSP <= regSP - 1;
dataMux <= outA;
mainFSM <= "0111";
when x"CD" => -- JSR opr16a
wr <= CPUread;
addrMUX <= addrPC;
regSP <= regSP - 1;
regPC <= temp;
mainFSM <= "0010";
when x"DD" => -- JSR oprx16,X
wr <= CPUread;
addrMUX <= addrPC;
regSP <= regSP - 1;
regPC <= temp + (x"00" & regX);
mainFSM <= "0010";
when others =>
mainFSM <= "0000";
end case; -- opcode
when "0111" => --##################### instruction cycle 6
case opcode is
when x"80" | x"82" => -- RTI, RTT
regPC(7 downto 0) <= datain;
addrMux <= addrPC;
mainFSM <= "0010";
when x"83" => -- SWI
regSP <= regSP - 1;
dataMux <= outHelp;
flagI <= '1';
if trace = '0' then
if irqRequest = '0' then
temp <= x"FFFC"; -- SWI vector
else
irqRequest <= '0';
temp <= x"FFFA"; -- IRQ vector
end if;
mainFSM <= "1000";
else
temp <= x"FFF8"; -- trace vector
mainFSM <= "1011";
end if;
when others =>
mainFSM <= "0000";
end case; -- opcode
when "1000" => --##################### instruction cycle 7
case opcode is
when x"83" => -- SWI
wr <= CPUread;
addrMux <= addrTM;
regSP <= regSP - 1;
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