📄 6805.vhd
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mainFSM <= "0101";
when x"10" | x"12" | x"14" | x"16" | x"18" | x"1A" | x"1C" | x"1E" | -- BSET n,opr8a
x"11" | x"13" | x"15" | x"17" | x"19" | x"1B" | x"1D" | x"1F" => -- BCLR n,opr8a
wr <= CPUwrite;
dataMux <= outHelp;
if opcode(0) = '0' then
help <= datain or mask1(conv_integer(opcode(3 downto 1)));
else
help <= datain and mask0(conv_integer(opcode(3 downto 1)));
end if;
mainFSM <= "0101";
when x"C0" | x"C1" | x"C2" | x"C3" | -- SUB opr16a, CMP opr16a, SBC opr16a, CPX opr16a
x"C4" | x"C5" | x"C6" | -- AND opr16a, BIT opr16a, LDA opr16a
x"C8" | x"C9" | x"CA" | x"CB" | -- EOR opr16a, ADC opr16a, ORA opr16a, ADD opr16a
x"CE" | -- LDX opr16a
x"D0" | x"D1" | x"D2" | x"D3" | -- SUB oprx16,X, CMP oprx16,X, SBC oprx16,X, CPX oprx16,X
x"D4" | x"D5" | x"D6" | -- AND oprx16,X, BIT oprx16,X, LDA oprx16,X
x"D8" | x"D9" | x"DA" | x"DB" | -- EOR oprx16,X, ADC oprx16,X, ORA oprx16,X, ADD oprx16,X
x"DE" | -- LDX oprx16,X
x"E0" | x"E1" | x"E2" | x"E3" | -- SUB oprx8,X, CMP oprx8,X, SBC oprx8,X, CPX oprx8,X
x"E4" | x"E5" | x"E6" | -- AND oprx8,X, BIT oprx8,X, LDA oprx8,X
x"E8" | x"E9" | x"EA" | x"EB" | -- EOR oprx8,X, ADC oprx8,X, ORA oprx8,X, ADD oprx8,X
x"EE" => -- LDX oprx8,X
temp(7 downto 0) <= datain;
case opcode(7 downto 4) is
when x"C" =>
addrMux <= addrTM;
when x"D" =>
addrMux <= addrX2;
when x"E" =>
addrMux <= addrX1;
when others =>
null;
end case;
regPC <= regPC + 1;
mainFSM <= "0101";
when x"CC" => -- JMP opr16a
regPC <= temp(15 downto 8) & datain;
mainFSM <= "0010";
when x"DC" => -- JMP oprx16,X
regPC <= (temp(15 downto 8) & datain) + (x"00" & regX);
mainFSM <= "0010";
when x"EC" => -- JMP oprx8,X
regPC <= (x"00" & datain) + (x"00" & regX);
mainFSM <= "0010";
when x"C7" => -- STA opr16a
wr <= CPUwrite;
flagN <= regA(7);
if regA = x"00" then
flagZ <= '1';
else
flagZ <= '0';
end if;
dataMux <= outA;
temp(7 downto 0) <= datain;
addrMux <= addrTM;
regPC <= regPC + 1;
mainFSM <= "0101";
when x"D7" => -- STA oprx16,X
wr <= CPUwrite;
flagN <= regA(7);
if regA = x"00" then
flagZ <= '1';
else
flagZ <= '0';
end if;
dataMux <= outA;
temp(7 downto 0) <= datain;
addrMux <= addrX2;
regPC <= regPC + 1;
mainFSM <= "0101";
when x"E7" => -- STA oprx8,X
wr <= CPUwrite;
flagN <= regA(7);
if regA = x"00" then
flagZ <= '1';
else
flagZ <= '0';
end if;
dataMux <= outA;
temp(7 downto 0) <= datain;
addrMux <= addrX1;
regPC <= regPC + 1;
mainFSM <= "0101";
when x"CF" => -- STX opr16a
wr <= CPUwrite;
flagN <= regX(7);
if regX = x"00" then
flagZ <= '1';
else
flagZ <= '0';
end if;
dataMux <= outX;
temp(7 downto 0) <= datain;
addrMux <= addrTM;
regPC <= regPC + 1;
mainFSM <= "0101";
when x"DF" => -- STX oprx16,X
wr <= CPUwrite;
flagN <= regX(7);
if regX = x"00" then
flagZ <= '1';
else
flagZ <= '0';
end if;
dataMux <= outX;
temp(7 downto 0) <= datain;
addrMux <= addrX2;
regPC <= regPC + 1;
mainFSM <= "0101";
when x"EF" => -- STX oprx8,X
wr <= CPUwrite;
flagN <= regX(7);
if regX = x"00" then
flagZ <= '1';
else
flagZ <= '0';
end if;
dataMux <= outX;
temp(7 downto 0) <= datain;
addrMux <= addrX1;
regPC <= regPC + 1;
mainFSM <= "0101";
when x"30" | x"60" | x"70" => -- NEG opr8a, NEG oprx8,X, NEG ,X
wr <= CPUwrite;
dataMux <= outHelp;
help <= x"00" - datain;
tres := x"00" - datain;
flagN <= tres(7);
if tres = x"00" then
flagZ <= '1';
flagC <= '0';
else
flagC <= '1';
flagZ <= '0';
end if;
mainFSM <= "0101";
when x"33" | x"63" | x"73" => -- COM opr8a, COM oprx8,X, COM ,X
wr <= CPUwrite;
dataMux <= outHelp;
help <= datain xor x"FF";
tres := datain xor x"FF";
flagC <= '1';
flagN <= tres(7);
if tres = x"00" then
flagZ <= '1';
else
flagZ <= '0';
end if;
mainFSM <= "0101";
when x"34" | x"64" | x"74" => -- LSR opr8a, LSR oprx8,X, LSR ,X
wr <= CPUwrite;
dataMux <= outHelp;
help <= "0" & datain(7 downto 1);
tres := "0" & datain(7 downto 1);
flagN <= '0';
flagC <= datain(0);
if tres = x"00" then
flagZ <= '1';
else
flagZ <= '0';
end if;
mainFSM <= "0101";
when x"36" | x"66" | x"76" => -- ROR opr8a, ROR oprx8,X, ROR ,X
wr <= CPUwrite;
dataMux <= outHelp;
help <= flagC & datain(7 downto 1);
tres := flagC & datain(7 downto 1);
flagN <= flagC;
flagC <= datain(0);
if tres = x"00" then
flagZ <= '1';
else
flagZ <= '0';
end if;
mainFSM <= "0101";
when x"37" | x"67" | x"77" => -- ASR opr8a, ASR oprx8,X, ASR ,X
wr <= CPUwrite;
dataMux <= outHelp;
help <= datain(7) & datain(7 downto 1);
tres := datain(7) & datain(7 downto 1);
flagN <= datain(7);
flagC <= datain(0);
if tres = x"00" then
flagZ <= '1';
else
flagZ <= '0';
end if;
mainFSM <= "0101";
when x"38" | x"68" | x"78" => -- LSL opr8a, LSL oprx8,X, LSL ,X
wr <= CPUwrite;
dataMux <= outHelp;
help <= datain(6 downto 0) & "0";
tres := datain(6 downto 0) & "0";
flagN <= datain(6);
flagC <= datain(7);
if tres = x"00" then
flagZ <= '1';
else
flagZ <= '0';
end if;
mainFSM <= "0101";
when x"39" | x"69" | x"79" => -- ROL opr8a, ROL oprx8,X, ROL ,X
wr <= CPUwrite;
dataMux <= outHelp;
help <= datain(6 downto 0) & flagC;
tres := datain(6 downto 0) & flagC;
flagN <= datain(6);
flagC <= datain(7);
if tres = x"00" then
flagZ <= '1';
else
flagZ <= '0';
end if;
mainFSM <= "0101";
when x"3A" | x"6A" | x"7A" => -- DEC opr8a, DEC oprx8,X, DEC ,X
wr <= CPUwrite;
dataMux <= outHelp;
help <= datain - 1;
tres := datain - 1;
flagN <= tres(7);
if tres = x"00" then
flagZ <= '1';
else
flagZ <= '0';
end if;
mainFSM <= "0101";
when x"3C" | x"6C" | x"7C" => -- INC opr8a, INC oprx8,X, INC ,X
wr <= CPUwrite;
dataMux <= outHelp;
help <= datain + 1;
tres := datain + 1;
flagN <= tres(7);
if tres = x"00" then
flagZ <= '1';
else
flagZ <= '0';
end if;
mainFSM <= "0101";
when x"3D" | x"6D" | x"7D" => -- TST opr8a, TST oprx8,X, TST ,X
flagN <= datain(7);
if datain = x"00" then
flagZ <= '1';
else
flagZ <= '0';
end if;
addrMux <= addrPC;
mainFSM <= "0010";
when x"3F" | x"6F" => -- CLR opr8a, CLR oprx8,X
wr <= CPUread;
addrMux <= addrPC;
mainFSM <= "0010";
when x"80" | x"82" => -- RTI, RTT
regA <= datain;
regSP <= regSP + 1;
mainFSM <= "0101";
when x"81" => -- RTS
regPC(7 downto 0) <= datain;
addrMux <= addrPC;
mainFSM <= "0010";
when x"83" => -- SWI
regSP <= regSP - 1;
dataMux <= outPCH;
mainFSM <= "0101";
when x"AD" | x"BD" | x"ED" => -- BSR rel, JSR opr8a, JSR oprx8,X
regSP <= regSP - 1;
dataMux <= outPCH;
mainFSM <= "0101";
when x"FD" => -- JSR ,X
regSP <= regSP - 1;
dataMux <= outTH;
mainFSM <= "0101";
when x"CD" | x"DD" => -- JSR opr16a, JSR oprx16,X
wr <= CPUwrite;
temp(7 downto 0) <= datain;
regPC <= regPC + 1;
addrMux <= addrSP;
dataMux <= outPCL;
mainFSM <= "0101";
when others =>
mainFSM <= "0000";
end case; -- opcode
when "0101" => --##################### instruction cycle 4
case opcode is
when x"00" | x"02" | x"04" | x"06" | x"08" | x"0A" | x"0C" | x"0E" | -- BRSET n,opr8a,rel
x"01" | x"03" | x"05" | x"07" | x"09" | x"0B" | x"0D" | x"0F" => -- BRCLR n,opr8a,rel
if (opcode(0) xor flagC) = '1' then
if datain(7) = '0' then
regPC <= regPC + (x"00" & datain) + x"0001";
else
regPC <= regPC + (x"FF" & datain) + x"0001";
end if;
else
regPC <= regPC + 1;
end if;
addrMux <= addrPC;
mainFSM <= "0010";
when x"10" | x"12" | x"14" | x"16" | x"18" | x"1A" | x"1C" | x"1E" | -- BSET n,opr8a
x"11" | x"13" | x"15" | x"17" | x"19" | x"1B" | x"1D" | x"1F" | -- BCLR n,opr8a
x"30" | x"33" | x"34" | x"36" | -- NEG opr8a, COM opr8a, LSR opr8a, ROR opr8a
x"37" | x"38" | x"39" | x"3A" | x"3C" | -- ASR opr8a, LSL opr8a, ROL opr8a, DEC opr8a, INC opr8a
x"60" | x"63" | x"64" | x"66" | x"67" | -- NEG oprx8,X, COM oprx8,X, LSR oprx8,X, ROR oprx8,X, ASR oprx8,X
x"68" | x"69" | x"6A" | x"6C" | -- LSL oprx8,X, ROL oprx8,X, DEC oprx8,X, INC oprx8,X
x"70" | x"73" | x"74" | x"76" | x"77" | x"78" | x"79" | -- NEG ,X, COM ,X, LSR ,X, ROR ,X, ASR ,X, LSL ,X, ROL ,X
x"7A" | x"7C" | -- DEC ,X, INC ,X
x"B7" | x"BF" | x"C7" | x"CF" | -- STA opr8a, STX opr8a, STA opr16a, STX opr16a
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