📄 6805.vhd
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else
flagZ <= '0';
end if;
regPC <= regPC + 1;
mainFSM <= "0010";
when x"5D" => -- TSTX
flagN <= regX(7);
if regX = x"00" then
flagZ <= '1';
else
flagZ <= '0';
end if;
regPC <= regPC + 1;
mainFSM <= "0010";
when x"5F" => -- CLRX
regX <= x"00";
flagN <= '0';
flagZ <= '1';
regPC <= regPC + 1;
mainFSM <= "0010";
when x"60" | x"63" | x"64" | x"66" | -- NEG oprx8,X, COM oprx8,X, LSR oprx8,X, ROR oprx8,X
x"67" | x"68" | x"69" | x"6A" | -- ASR oprx8,X, LSL oprx8,X, ROL oprx8,X, DEC oprx8,X
x"6C" | x"6D" | x"6F" => -- INC oprx8,X, TST oprx8,X, CLR oprx8,X
temp <= x"00" & regX;
regPC <= regPC + 1;
mainFSM <= "0011";
when x"7F" => -- CLR ,X
flagN <= '0';
flagZ <= '1';
addrMux <= addrHX;
dataMux <= outHelp;
wr <= CPUwrite;
help <= x"00";
regPC <= regPC + 1;
mainFSM <= "0011";
when x"80" | x"81" => -- RTI, RTS
regSP <= regSP + 1;
addrMux <= addrSP;
mainFSM <= "0011";
when x"83" => -- SWI
regPC <= regPC + 1;
addrMux <= addrSP;
mainFSM <= "0011";
when x"8E" => -- STOP currently unsupported
regPC <= regPC + 1;
mainFSM <= "0010";
when x"8F" => -- WAIT currently unsupported
regPC <= regPC + 1;
mainFSM <= "0010";
when x"97" => -- TAX
regX <= regA;
regPC <= regPC + 1;
mainFSM <= "0010";
when x"98" | x"99" => -- CLC, SEC
flagC <= datain(0);
regPC <= regPC + 1;
mainFSM <= "0010";
when x"9A" | x"9B" => -- CLI, SEI ATTENTION!!!
flagI <= datain(0);
regPC <= regPC + 1;
mainFSM <= "0010";
when x"9C" => -- RSP
regSP <= x"00FF";
regPC <= regPC + 1;
mainFSM <= "0010";
when x"31" | x"41" | x"35" | x"3B" | x"45" |
x"4B" | x"4E" | x"51" | x"52" | x"55" |
x"5B" | x"5E" | x"61" | x"62" | x"65" |
x"6B" | x"6E" | x"71" | x"72" | x"75" | x"7B" | x"7E" |
x"84" | x"85" | x"86" | x"87" | x"88" |
x"89" | x"8A" | x"8B" | x"8C" | x"8D" |
x"90" | x"91" | x"92" | x"93" | x"94" | x"95" | x"9D" | x"9E" |
x"A7" | x"AC" | x"AF" => -- NOP
regPC <= regPC + 1;
mainFSM <= "0010";
when x"9F" => -- TXA
regA <= regX;
regPC <= regPC + 1;
mainFSM <= "0010";
when x"AD" | x"BD" | x"ED" => -- BSR rel, JSR opr8a, JSR oprx8,X
temp <= regPC + 2;
regPC <= regPC + 1;
mainFSM <= "0011";
when x"CD" | x"DD" => -- JSR opr16a, JSR oprx16,X
temp <= regPC + 3;
regPC <= regPC + 1;
mainFSM <= "0011";
when x"FD" => -- JSR ,X
temp <= regPC + 1;
wr <= CPUwrite;
addrMux <= addrSP;
dataMux <= outTL;
regPC <= regPC + 1;
mainFSM <= "0100";
when others =>
mainFSM <= "0000";
end case; -- datain
end if; -- trace = '1'
when "0011" => --##################### instruction cycle 2
case opcode is
when x"00" | x"02" | x"04" | x"06" | x"08" | x"0A" | x"0C" | x"0E" | -- BRSET n,opr8a,rel
x"01" | x"03" | x"05" | x"07" | x"09" | x"0B" | x"0D" | x"0F" | -- BRCLR n,opr8a,rel
x"10" | x"12" | x"14" | x"16" | x"18" | x"1A" | x"1C" | x"1E" | -- BSET n,opr8a
x"11" | x"13" | x"15" | x"17" | x"19" | x"1B" | x"1D" | x"1F" | -- BCLR n,opr8a
x"30" | x"33" | x"34" | x"36" | -- NEG opr8a, COM opr8a, LSR opr8a, ROR opr8a
x"37" | x"38" | x"39" | x"3A" | x"3C" | -- ASR opr8a, LSL opr8a, ROL opr8a, DEC opr8a, INC opr8a
x"3D" => -- TST opr8a
temp(7 downto 0) <= datain;
addrMux <= addrTM;
regPC <= regPC + 1;
mainFSM <= "0100";
when x"C0" | x"C1" | x"C2" | x"C3" | -- SUB opr16a, CMP opr16a, SBC opr16a, CPX opr16a
x"C4" | x"C5" | x"C6" | x"C7" | -- AND opr16a, BIT opr16a, LDA opr16a, STA opr16a
x"C8" | x"C9" | x"CA" | x"CB" | -- EOR opr16a, ADC opr16a, ORA opr16a, ADD opr16a
x"CC" | x"CE" | x"CF" | -- JMP opr16a, LDX opr16a, STX opr16a
x"D0" | x"D1" | x"D2" | x"D3" | -- SUB oprx16,X, CMP oprx16,X, SBC oprx16,X, CPX oprx16,X
x"D4" | x"D5" | x"D6" | x"D7" | -- AND oprx16,X, BIT oprx16,X, LDA oprx16,X, STA oprx16,X
x"D8" | x"D9" | x"DA" | x"DB" | -- EOR oprx16,X, ADC oprx16,X, ORA oprx16,X, ADD oprx16,X
x"DC" | x"DE" | x"DF" => -- JMP oprx16,X, LDX oprx16,X, STX oprx16,X
temp(15 downto 8) <= datain;
regPC <= regPC + 1;
mainFSM <= "0100";
when x"B7" => -- STA opr8a
wr <= CPUwrite;
dataMux <= outA;
temp(7 downto 0) <= datain;
addrMux <= addrTM;
regPC <= regPC + 1;
mainFSM <= "0101";
when x"BF" => -- STX opr8a
wr <= CPUwrite;
dataMux <= outX;
temp(7 downto 0) <= datain;
addrMux <= addrTM;
regPC <= regPC + 1;
mainFSM <= "0101";
when x"B0" | x"B1" | x"B2" | x"B3" | -- SUB opr8a, CMP opr8a, SBC opr8a, CPX opr8a
x"B4" | x"B5" | x"B6" | -- AND opr8a, BIT opr8a, LDA opr8a
x"B8" | x"B9" | x"BA" | x"BB" | -- EOR opr8a, ADC opr8a, ORA opr8a, ADD opr8a
x"BE" => -- LDX opr8a
temp(7 downto 0) <= datain;
addrMux <= addrTM;
regPC <= regPC + 1;
mainFSM <= "0101";
when x"20" => -- BRA
if datain(7) = '0' then
regPC <= regPC + (x"00" & datain) + x"0001";
else
regPC <= regPC + (x"FF" & datain) + x"0001";
end if;
mainFSM <= "0010";
when x"21" => -- BRN
regPC <= regPC + 1;
mainFSM <= "0010";
when x"22" | x"23" => -- BHI, BLS
if (flagC or flagZ) = opcode(0) then
if datain(7) = '0' then
regPC <= regPC + (x"00" & datain) + x"0001";
else
regPC <= regPC + (x"FF" & datain) + x"0001";
end if;
else
regPC <= regPC + 1;
end if;
mainFSM <= "0010";
when x"24" | x"25" => -- BCC, BCS
if (flagC = opcode(0)) then
if datain(7) = '0' then
regPC <= regPC + (x"00" & datain) + x"0001";
else
regPC <= regPC + (x"FF" & datain) + x"0001";
end if;
else
regPC <= regPC + 1;
end if;
mainFSM <= "0010";
when x"26" | x"27" => -- BNE, BEQ
if (flagZ = opcode(0)) then
if datain(7) = '0' then
regPC <= regPC + (x"00" & datain) + x"0001";
else
regPC <= regPC + (x"FF" & datain) + x"0001";
end if;
else
regPC <= regPC + 1;
end if;
mainFSM <= "0010";
when x"28" | x"29" => -- BHCC, BHCS
if (flagH = opcode(0)) then
if datain(7) = '0' then
regPC <= regPC + (x"00" & datain) + x"0001";
else
regPC <= regPC + (x"FF" & datain) + x"0001";
end if;
else
regPC <= regPC + 1;
end if;
mainFSM <= "0010";
when x"2A" | x"2B" => -- BPL, BMI
if (flagN = opcode(0)) then
if datain(7) = '0' then
regPC <= regPC + (x"00" & datain) + x"0001";
else
regPC <= regPC + (x"FF" & datain) + x"0001";
end if;
else
regPC <= regPC + 1;
end if;
mainFSM <= "0010";
when x"2C" | x"2D" => -- BMC, BMS
if (flagI = opcode(0)) then
if datain(7) = '0' then
regPC <= regPC + (x"00" & datain) + x"0001";
else
regPC <= regPC + (x"FF" & datain) + x"0001";
end if;
else
regPC <= regPC + 1;
end if;
mainFSM <= "0010";
when x"2E" | x"2F" => -- BIL, BIH
if (irq = opcode(0)) then
if datain(7) = '0' then
regPC <= regPC + (x"00" & datain) + x"0001";
else
regPC <= regPC + (x"FF" & datain) + x"0001";
end if;
else
regPC <= regPC + 1;
end if;
mainFSM <= "0010";
when x"3F" | x"6F" => -- CLR opr8a, CLR oprx8,X
wr <= CPUwrite;
case opcode is
when x"3F" =>
temp(7 downto 0) <= datain;
when x"6F" =>
temp <= temp + (x"00" & datain);
when others =>
temp <= x"0000";
end case;
addrMux <= addrTM;
dataMux <= outHelp;
flagZ <= '1';
flagN <= '0';
help <= x"00";
regPC <= regPC + 1;
mainFSM <= "0100";
when x"60" | x"63" | x"64" | x"66" | -- NEG oprx8,X, COM oprx8,X, LSR oprx8,X, ROR oprx8,X
x"67" | x"68" | x"69" | x"6A" | -- ASR oprx8,X, LSL oprx8,X, ROL oprx8,X, DEC oprx8,X
x"6C" | x"6D" => -- INC oprx8,X, TST oprx8,X
temp <= temp + (x"00" & datain);
regPC <= regPC + 1;
addrMux <= addrTM;
mainFSM <= "0100";
when x"7F" => -- CLR ,X
wr <= CPUread;
addrMux <= addrPC;
mainFSM <= "0010";
when x"80" | x"82" => -- RTI, RTT
flagH <= datain(4);
flagI <= datain(3); ------- PLEASE RESTORE AT LATER TIME
flagN <= datain(2);
flagZ <= datain(1);
flagC <= datain(0);
regSP <= regSP + 1;
mainFSM <= "0100";
when x"81" => -- RTS
regPC(15 downto 8) <= datain;
regSP <= regSP + 1;
mainFSM <= "0100";
when x"83" => -- SWI
wr <= CPUwrite;
dataMux <= outPCL;
mainFSM <= "0100";
when x"AD" | x"BD" | x"ED" => -- BSR rel, JSR opr8a, JSR oprx8,X
regPC <= regPC + 1;
wr <= CPUwrite;
help <= datain;
addrMux <= addrSP;
dataMux <= outPCL;
mainFSM <= "0100";
when x"BC" => -- JMP opr8a
regPC <= (x"00" & datain);
mainFSM <= "0010";
when x"CD" | x"DD" => -- JSR opr16a, JSR oprx16,X
temp(15 downto 8) <= datain;
regPC <= regPC + 1;
mainFSM <= "0100";
when others =>
mainFSM <= "0000";
end case; -- opcode
when "0100" => --##################### instruction cycle 3
case opcode is
when x"00" | x"02" | x"04" | x"06" | x"08" | x"0A" | x"0C" | x"0E" | -- BRSET n,opr8a,rel
x"01" | x"03" | x"05" | x"07" | x"09" | x"0B" | x"0D" | x"0F" => -- BRCLR n,opr8a,rel
if (datain and mask1(conv_integer(opcode(3 downto 1)))) /= x"00" then
flagC <= '1';
else
flagC <= '0';
end if;
addrMux <= addrPC;
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