📄 6805.vhd
字号:
x"01" | x"03" | x"05" | x"07" | x"09" | x"0B" | x"0D" | x"0F" | -- BRCLR n,opr8a,rel
x"10" | x"12" | x"14" | x"16" | x"18" | x"1A" | x"1C" | x"1E" | -- BSET n,opr8a
x"11" | x"13" | x"15" | x"17" | x"19" | x"1B" | x"1D" | x"1F" | -- BCLR n,opr8a
x"30" | x"33" | x"34" | -- NEG opr8a, COM opr8a, LSR opr8a
x"36" | x"37" | x"38" | -- ROR opr8a, ASR opr8a, LSL opr8a
x"39" | x"3A" | x"3C" | -- ROL opr8a, DEC opr8a, INC opr8a
x"3D" | x"3F" | -- TST opr8a, CLR opr8a
x"B0" | x"B1" | x"B2" | x"B3" | -- SUB opr8a, CMP opr8a, SBC opr8a, CPX opr8a
x"B4" | x"B5" | x"B6" | x"B7" | -- AND opr8a, BIT opr8a, LDA opr8a, STA opr8a
x"B8" | x"B9" | x"BA" | x"BB" | -- EOR opr8a, ADC opr8a, ORA opr8a, ADD opr8a
x"BC" | x"BE" | x"BF" => -- JMP opr8a, LDX opr8a, STX opr8a
temp <= x"0000";
regPC <= regPC + 1;
mainFSM <= "0011";
when x"20" | x"21" | x"22" | x"23" | x"24" | x"25" | x"26" | x"27" |
x"28" | x"29" | x"2A" | x"2B" | x"2C" | x"2D" | x"2E" | x"2F" | -- branches
x"C0" | x"C1" | x"C2" | x"C3" | -- SUB opr16a, CMP opr16a, SBC opr16a, CPX opr16a
x"C4" | x"C5" | x"C6" | x"C7" | -- AND opr16a, BIT opr16a, LDA opr16a, STA opr16a
x"C8" | x"C9" | x"CA" | x"CB" | -- EOR opr16a, ADC opr16a, ORA opr16a, ADD opr16a
x"CC" | x"CE" | x"CF" | -- JMP opr16a, LDX opr16a, STX opr16a
x"D0" | x"D1" | x"D2" | x"D3" | -- SUB oprx16,X, CMP oprx16,X, SBC oprx16,X, CPX oprx16,X
x"D4" | x"D5" | x"D6" | x"D7" | -- AND oprx16,X, BIT oprx16,X, LDA oprx16,X, STA oprx16,X
x"D8" | x"D9" | x"DA" | x"DB" | -- EOR oprx16,X, ADC oprx16,X, ORA oprx16,X, ADD oprx16,X
x"DC" | x"DE" | x"DF" => -- JMP oprx16,X, LDX oprx16,X, STX oprx16,X
regPC <= regPC + 1;
mainFSM <= "0011";
when x"70" | x"73" | x"74" | x"76" | x"77" | -- NEG ,X, COM ,X, LSR ,X, ROR ,X, ASR ,X
x"78" | x"79" | x"7A" | x"7C" | x"7D" => -- LSL ,X, ROL ,X, DEC ,X, INC ,X, TXT ,X
addrMux <= addrHX;
regPC <= regPC + 1;
mainFSM <= "0100";
when x"A0" | x"A1" | x"A2" | x"A3" | -- SUB #opr8i, CMP #opr8i, SBC #opr8i, CPX #opr8i
x"A4" | x"A5" | x"A6" | -- AND #opr8i, BIT #opr8i, LDA #opr8i
x"A8" | x"A9" | x"AA" | x"AB" | -- EOR #opr8i, ADC #opr8i, ORA #opr8i, ADD #opr8i
x"AE" => -- LDX #opr8i
regPC <= regPC + 1;
mainFSM <= "0101";
when x"E0" | x"E1" | x"E2" | x"E3" | -- SUB oprx8,X, CMP oprx8,X, SBC oprx8,X, CPX oprx8,X
x"E4" | x"E5" | x"E6" | x"E7" | -- AND oprx8,X, BIT oprx8,X, LDA oprx8,X, STA oprx8,X
x"E8" | x"E9" | x"EA" | x"EB" | -- EOR oprx8,X, ADC oprx8,X, ORA oprx8,X, ADD oprx8,X
x"EC" | x"EE" | x"EF" => -- JMP oprx8,X, LDX oprx8,X, STX oprx8,X
regPC <= regPC + 1;
mainFSM <= "0100";
when x"F0" | x"F1" | x"F2" | x"F3" | -- SUB ,X, CMP ,X, SBC ,X, CPX ,X
x"F4" | x"F5" | x"F6" | -- AND ,X, BIT ,X, LDA ,X
x"F8" | x"F9" | x"FA" | x"FB" | -- EOR ,X, ADC ,X, ORA ,X, ADD ,X
x"FE" => -- LDX ,X
addrMux <= addrHX;
regPC <= regPC + 1;
mainFSM <= "0101";
when x"FC" => -- JMP ,X
regPC <= x"00" & regX;
mainFSM <= "0010";
when x"F7" => -- STA ,X
wr <= CPUwrite;
flagN <= regA(7);
if regA = x"00" then
flagZ <= '1';
else
flagZ <= '0';
end if;
dataMux <= outA;
addrMux <= addrHX;
regPC <= regPC + 1;
mainFSM <= "0101";
when x"FF" => -- STX ,X
wr <= CPUwrite;
flagN <= regX(7);
if regX = x"00" then
flagZ <= '1';
else
flagZ <= '0';
end if;
dataMux <= outX;
addrMux <= addrHX;
regPC <= regPC + 1;
mainFSM <= "0101";
when x"40" => -- NEGA
regA <= x"00" - regA;
tres := x"00" - regA;
flagN <= tres(7);
if tres = x"00" then
flagZ <= '1';
flagC <= '0';
else
flagC <= '1';
flagZ <= '0';
end if;
regPC <= regPC + 1;
mainFSM <= "0010";
when x"42" => -- MUL
flagH <= '0';
flagC <= '0';
regA <= prod(7 downto 0);
regX <= prod(15 downto 8);
regPC <= regPC + 1;
mainFSM <= "0010";
when x"43" => -- COMA
regA <= regA xor x"FF";
tres := regA xor x"FF";
flagC <= '1';
flagN <= tres(7);
if tres = x"00" then
flagZ <= '1';
else
flagZ <= '0';
end if;
regPC <= regPC + 1;
mainFSM <= "0010";
when x"44" => -- LSRA
regA <= "0" & regA(7 downto 1);
tres := "0" & regA(7 downto 1);
flagN <= '0';
flagC <= regA(0);
if tres = x"00" then
flagZ <= '1';
else
flagZ <= '0';
end if;
regPC <= regPC + 1;
mainFSM <= "0010";
when x"46" => -- RORA
regA <= flagC & regA(7 downto 1);
tres := flagC & regA(7 downto 1);
flagN <= flagC;
flagC <= regA(0);
if tres = x"00" then
flagZ <= '1';
else
flagZ <= '0';
end if;
regPC <= regPC + 1;
mainFSM <= "0010";
when x"47" => -- ASRA
regA <= regA(7) & regA(7 downto 1);
tres := regA(7) & regA(7 downto 1);
flagN <= regA(7);
flagC <= regA(0);
if tres = x"00" then
flagZ <= '1';
else
flagZ <= '0';
end if;
regPC <= regPC + 1;
mainFSM <= "0010";
when x"48" => -- LSLA
regA <= regA(6 downto 0) & "0";
tres := regA(6 downto 0) & "0";
flagN <= regA(6);
flagC <= regA(7);
if tres = x"00" then
flagZ <= '1';
else
flagZ <= '0';
end if;
regPC <= regPC + 1;
mainFSM <= "0010";
when x"49" => -- ROLA
regA <= regA(6 downto 0) & flagC;
tres := regA(6 downto 0) & flagC;
flagN <= regA(6);
flagC <= regA(7);
if tres = x"00" then
flagZ <= '1';
else
flagZ <= '0';
end if;
regPC <= regPC + 1;
mainFSM <= "0010";
when x"4A" => -- DECA
regA <= regA - 1;
tres := regA - 1;
flagN <= tres(7);
if tres = x"00" then
flagZ <= '1';
else
flagZ <= '0';
end if;
regPC <= regPC + 1;
mainFSM <= "0010";
when x"4C" => -- INCA
regA <= regA + 1;
tres := regA + 1;
flagN <= tres(7);
if tres = x"00" then
flagZ <= '1';
else
flagZ <= '0';
end if;
regPC <= regPC + 1;
mainFSM <= "0010";
when x"4D" => -- TSTA
flagN <= regA(7);
if regA = x"00" then
flagZ <= '1';
else
flagZ <= '0';
end if;
regPC <= regPC + 1;
mainFSM <= "0010";
when x"4F" => -- CLRA
regA <= x"00";
flagN <= '0';
flagZ <= '1';
regPC <= regPC + 1;
mainFSM <= "0010";
when x"50" => -- NEGX
regX <= x"00" - regX;
tres := x"00" - regX;
flagN <= tres(7);
if tres = x"00" then
flagZ <= '1';
flagC <= '0';
else
flagC <= '1';
flagZ <= '0';
end if;
regPC <= regPC + 1;
mainFSM <= "0010";
when x"53" => -- COMX
regX <= regX xor x"FF";
tres := regX xor x"FF";
flagC <= '1';
flagN <= tres(7);
if tres = x"00" then
flagZ <= '1';
else
flagZ <= '0';
end if;
regPC <= regPC + 1;
mainFSM <= "0010";
when x"54" => -- LSRX
regX <= "0" & regX(7 downto 1);
tres := "0" & regX(7 downto 1);
flagN <= '0';
flagC <= regX(0);
if tres = x"00" then
flagZ <= '1';
else
flagZ <= '0';
end if;
regPC <= regPC + 1;
mainFSM <= "0010";
when x"56" => -- RORX
regX <= flagC & regX(7 downto 1);
tres := flagC & regX(7 downto 1);
flagN <= flagC;
flagC <= regX(0);
if tres = x"00" then
flagZ <= '1';
else
flagZ <= '0';
end if;
regPC <= regPC + 1;
mainFSM <= "0010";
when x"57" => -- ASRX
regX <= regX(7) & regX(7 downto 1);
tres := regX(7) & regX(7 downto 1);
flagN <= regX(7);
flagC <= regX(0);
if tres = x"00" then
flagZ <= '1';
else
flagZ <= '0';
end if;
regPC <= regPC + 1;
mainFSM <= "0010";
when x"58" => -- LSLX
regX <= regX(6 downto 0) & "0";
tres := regX(6 downto 0) & "0";
flagN <= regX(6);
flagC <= regX(7);
if tres = x"00" then
flagZ <= '1';
else
flagZ <= '0';
end if;
regPC <= regPC + 1;
mainFSM <= "0010";
when x"59" => -- ROLX
regX <= regX(6 downto 0) & flagC;
tres := regX(6 downto 0) & flagC;
flagN <= regX(6);
flagC <= regX(7);
if tres = x"00" then
flagZ <= '1';
else
flagZ <= '0';
end if;
regPC <= regPC + 1;
mainFSM <= "0010";
when x"5A" => -- DECX
regX <= regX(7 downto 0) - 1;
tres := regX(7 downto 0) - 1;
flagN <= tres(7);
if tres = x"00" then
flagZ <= '1';
else
flagZ <= '0';
end if;
regPC <= regPC + 1;
mainFSM <= "0010";
when x"5C" => -- INCX
regX <= regX(7 downto 0) + 1;
tres := regX(7 downto 0) + 1;
flagN <= tres(7);
if tres = x"00" then
flagZ <= '1';
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