p3544sio.h

vxworks practise_3544.rar 的驱动

/* p3544Sio.h - header file for binary interface Intel 8250 UART driver */

/* Copyright 1984-1993 Wind River Systems, Inc. */

/*
modification history
--------------------
01d,03jun98,hdn  changed p3544_IIR_MASK from 6 to 7 to fix the TX-int problem.
01c,22may97,db	 added macros for all p3544 registers(SPR #7542).
01b,15jun95,ms   updated for new driver.
01a,15mar95,myz  written (from p3544Serial.h)
*/

#ifndef	__INCp3544Sioh
#define	__INCp3544Sioh

#ifdef __cplusplus
extern "C" {
#endif


#ifndef _ASMLANGUAGE

#include "vxWorks.h"
#include "sioLib.h"
//#include "pciConfigLib.h"
/* channel data structure  */

typedef struct 		/* p3544_CHAN */
    {
    SIO_DRV_FUNCS * pDrvFuncs;       /* driver functions */

    STATUS      (*getTxChar) ();     /* pointer to xmitr function */
    STATUS      (*putRcvChar) ();    /* pointer tp rcvr function */
    void *      getTxArg;
    void *      putRcvArg;

    UINT32  ioBase;                 /* io base addr */
    UINT16  channelMode;             /* SIO_MODE_[INT | POLL] */
 
    ULONG   lcr;                     /* UART line control register */
    ULONG   lsr;                     /* UART line status register */
    ULONG   mcr;                     /* UART modem control register */
    ULONG   msr;                     /* UART modem status register */
    ULONG   ier;                     /* UART interrupt enable register */
    ULONG   iir;                     /* UART interrupt ID register */
    ULONG   scr;		     /* I/O: Scratch Register */
    ULONG   fcr;		     /* Out: FIFO Control Register */
    ULONG   efr;		     /* I/O: Extended Features Register */
				     /* (DLAB=1, 16C660 only) */
    ULONG   dll;                     /* UART baud rate register */
    ULONG   dlm;                     /* UART baud rate register */
    ULONG   data;                     /* In:  Receive Transmit buffer (DLAB=0) */
  
    ULONG   options;		     /* UART hardware options */
    UINT16  port_type;		     /* These are the supported serial types*/
    ULONG   async_flags;       
   
    } p3544_CHAN;



typedef struct			/* BAUD */
    {
    int rate;		/* a baud rate */
    int preset;		/* counter preset value to write to DUSCC_CTPR[HL]A */
    } p3544_BAUD;
    
struct serial_uart_config {
	char	*name;
	int	dfl_xmit_fifo_size;
	int	flags;
};
/* register definitions */

#define p3544_UART_DATA	0	/* In:  Receive Transmit buffer (DLAB=0) */
#define p3544_UART_DLL	0	/* Out: Divisor Latch Low (DLAB=1) */
#define p3544_UART_DLM	1	/* Out: Divisor Latch High (DLAB=1) */
        
#define p3544_UART_IER	1	/* Out: Interrupt Enable Register */
#define p3544_UART_IIR	2	/* In:  Interrupt ID Register */
#define p3544_UART_FCR	2	/* Out: FIFO Control Register */
#define p3544_UART_EFR	2	/* I/O: Extended Features Register */
				        /* (DLAB=1, 16C660 only) */
       
#define p3544_UART_LCR	3	/* Out: Line Control Register */
#define p3544_UART_MCR	4	/* Out: Modem Control Register */
#define p3544_UART_LSR	5	/* In:  Line Status Register */
#define p3544_UART_MSR	6	/* In:  Modem Status Register */
#define p3544_UART_SCR	7	/* I/O: Scratch Register */


/*
 * These are the definitions for the FIFO Control Register
 * (16650 only)
 */
#define UART_FCR_ENABLE_FIFO	0x01 /* Enable the FIFO */
#define UART_FCR_CLEAR_RCVR	0x02 /* Clear the RCVR FIFO */
#define UART_FCR_CLEAR_XMIT	0x04 /* Clear the XMIT FIFO */
#define UART_FCR_DMA_SELECT	0x08 /* For DMA applications */
#define UART_FCR_TRIGGER_MASK	0xC0 /* Mask for the FIFO trigger range */
#define UART_FCR_TRIGGER_1	0x00 /* Mask for trigger set at 1 */
#define UART_FCR_TRIGGER_4	0x40 /* Mask for trigger set at 4 */
#define UART_FCR_TRIGGER_8	0x80 /* Mask for trigger set at 8 */
#define UART_FCR_TRIGGER_14	0xC0 /* Mask for trigger set at 14 */
/* 16650 redefinitions */
#define UART_FCR6_R_TRIGGER_8	0x00 /* Mask for receive trigger set at 1 */
#define UART_FCR6_R_TRIGGER_16	0x40 /* Mask for receive trigger set at 4 */
#define UART_FCR6_R_TRIGGER_24  0x80 /* Mask for receive trigger set at 8 */
#define UART_FCR6_R_TRIGGER_28	0xC0 /* Mask for receive trigger set at 14 */
#define UART_FCR6_T_TRIGGER_16	0x00 /* Mask for transmit trigger set at 16 */
#define UART_FCR6_T_TRIGGER_8	0x10 /* Mask for transmit trigger set at 8 */
#define UART_FCR6_T_TRIGGER_24  0x20 /* Mask for transmit trigger set at 24 */
#define UART_FCR6_T_TRIGGER_30	0x30 /* Mask for transmit trigger set at 30 */
/* TI 16750 definitions */
#define UART_FCR7_64BYTE	0x20 /* Go into 64 byte mode */

/*
 * These are the definitions for the Line Control Register
 * 
 * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting 
 * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
 */
#define UART_LCR_DLAB	0x80	/* Divisor latch access bit */
#define UART_LCR_SBC	0x40	/* Set break control */
#define UART_LCR_SPAR	0x20	/* Stick parity (?) */
#define UART_LCR_EPAR	0x10	/* Even parity select */
#define UART_LCR_PARITY	0x08	/* Parity Enable */
#define UART_LCR_STOP	0x04	/* Stop bits: 0=1 stop bit, 1= 2 stop bits */
#define UART_LCR_WLEN5  0x00	/* Wordlength: 5 bits */
#define UART_LCR_WLEN6  0x01	/* Wordlength: 6 bits */
#define UART_LCR_WLEN7  0x02	/* Wordlength: 7 bits */
#define UART_LCR_WLEN8  0x03	/* Wordlength: 8 bits */

/*
 * These are the definitions for the Line Status Register
 */
#define UART_LSR_TEMT	0x40	/* Transmitter empty */
#define UART_LSR_THRE	0x20	/* Transmit-hold-register empty */
#define UART_LSR_BI	0x10	/* Break interrupt indicator */
#define UART_LSR_FE	0x08	/* Frame error indicator */
#define UART_LSR_PE	0x04	/* Parity error indicator */
#define UART_LSR_OE	0x02	/* Overrun error indicator */
#define UART_LSR_DR	0x01	/* Receiver data ready */

/*
 * These are the definitions for the Interrupt Identification Register
 */
#define UART_IIR_NO_INT	0x01	/* No interrupts pending */
#define UART_IIR_ID	    0x06	/* Mask for the interrupt ID */

#define UART_IIR_MSI	0x00	/* Modem status interrupt */
#define UART_IIR_THRI	0x02	/* Transmitter holding register empty */
#define UART_IIR_RDI	0x04	/* Receiver data interrupt */
#define UART_IIR_RLSI	0x06	/* Receiver line status interrupt */

/*
 * These are the definitions for the Interrupt Enable Register
 */
#define UART_IER_MSI	0x08	/* Enable Modem status interrupt */
#define UART_IER_RLSI	0x04	/* Enable receiver line status interrupt */
#define UART_IER_THRI	0x02	/* Enable Transmitter holding register int. */
#define UART_IER_RDI	0x01	/* Enable receiver data interrupt */
/*
 * Sleep mode for ST16650 and TI16750.
 * Note that for 16650, EFR-bit 4 must be selected as well.
 */
#define UART_IERX_SLEEP  0x10	/* Enable sleep mode */

/*
 * These are the definitions for the Modem Control Register
 */
#define UART_MCR_LOOP	0x10	/* Enable loopback test mode */
#define UART_MCR_OUT2	0x08	/* Out2 complement */
#define UART_MCR_OUT1	0x04	/* Out1 complement */
#define UART_MCR_RTS	0x02	/* RTS complement */
#define UART_MCR_DTR	0x01	/* DTR complement */

/*
 * These are the definitions for the Modem Status Register
 */
#define UART_MSR_DCD	0x80	/* Data Carrier Detect */
#define UART_MSR_RI	0x40	/* Ring Indicator */
#define UART_MSR_DSR	0x20	/* Data Set Ready */
#define UART_MSR_CTS	0x10	/* Clear to Send */
#define UART_MSR_DDCD	0x08	/* Delta DCD */
#define UART_MSR_TERI	0x04	/* Trailing edge ring indicator */
#define UART_MSR_DDSR	0x02	/* Delta DSR */
#define UART_MSR_DCTS	0x01	/* Delta CTS */
#define UART_MSR_ANY_DELTA 0x0F	/* Any of the delta bits! */

/*
 * These are the definitions for the Extended Features Register
 * (StarTech 16C660 only, when DLAB=1)
 */
#define UART_EFR_CTS	0x80	/* CTS flow control */
#define UART_EFR_RTS	0x40	/* RTS flow control */
#define UART_EFR_SCD	0x20	/* Special character detect */
#define UART_EFR_ECB	0x10	/* Enhanced control bit */
/*
 * the low four bits control software flow control
 */






#define UART_CLEAR_FIFO		0x01
#define UART_USE_FIFO		0x02
#define UART_STARTECH		0x04

/*
 * Definitions for async_struct (and serial_struct) flags field
 */
#define ASYNC_HUP_NOTIFY 0x0001 /* Notify getty on hangups and closes 
				   on the callout port */
#define ASYNC_FOURPORT  0x0002	/* Set OU1, OUT2 per AST Fourport settings */
#define ASYNC_SAK	0x0004	/* Secure Attention Key (Orange book) */
#define ASYNC_SPLIT_TERMIOS 0x0008 /* Separate termios for dialin/callout */

#define ASYNC_SPD_MASK	0x1030
#define ASYNC_SPD_HI	0x0010	/* Use 56000 instead of 38400 bps */

#define ASYNC_SPD_VHI	0x0020  /* Use 115200 instead of 38400 bps */
#define ASYNC_SPD_CUST	0x0030  /* Use user-specified divisor */

#define ASYNC_SKIP_TEST	0x0040 /* Skip UART test during autoconfiguration */
#define ASYNC_AUTO_IRQ   0x0080 /* Do automatic IRQ during autoconfiguration */
#define ASYNC_SESSION_LOCKOUT 0x0100 /* Lock out cua opens based on session */
#define ASYNC_PGRP_LOCKOUT    0x0200 /* Lock out cua opens based on pgrp */
#define ASYNC_CALLOUT_NOHUP   0x0400 /* Don't do hangups for cua device */

#define ASYNC_HARDPPS_CD	0x0800	/* Call hardpps when CD goes high  */

#define ASYNC_SPD_SHI	0x1000	/* Use 230400 instead of 38400 bps */
#define ASYNC_SPD_WARP	0x1010	/* Use 460800 instead of 38400 bps */

#define ASYNC_LOW_LATENCY 0x2000 /* Request low latency behaviour */

#define ASYNC_BUGGY_UART  0x4000 /* This is a buggy UART, skip some safety
				  * checks.  Note: can be dangerous! */

#define ASYNC_AUTOPROBE	 0x8000 /* Port was autoprobed by PCI or PNP code */

#define ASYNC_FLAGS	0x7FFF	/* Possible legal async flags */
#define ASYNC_USR_MASK	0x3430	/* Legal flags that non-privileged
				 * users can set or reset */

/* Internal flags used only by kernel/chr_drv/serial.c */
#define ASYNC_INITIALIZED	0x80000000 /* Serial port was initialized */
#define ASYNC_CALLOUT_ACTIVE	0x40000000 /* Call out device is active */
#define ASYNC_NORMAL_ACTIVE	0x20000000 /* Normal device is active */
#define ASYNC_BOOT_AUTOCONF	0x10000000 /* Autoconfigure port on bootup */
#define ASYNC_CLOSING		0x08000000 /* Serial port is closing */
#define ASYNC_CTS_FLOW		0x04000000 /* Do CTS flow control */
#define ASYNC_CHECK_CD		0x02000000 /* i.e., CLOCAL */
#define ASYNC_SHARE_IRQ		0x01000000 /* for multifunction cards
					     --- no longer used */
#define ASYNC_CONS_FLOW		0x00800000 /* flow control for console  */

#define ASYNC_BOOT_ONLYMCA	0x00400000 /* Probe only if MCA bus */
#define ASYNC_INTERNAL_FLAGS	0xFFC00000 /* Internal flags */
/*
 * These are the supported serial types.
 */
#define PORT_UNKNOWN	0
#define PORT_8250	1
#define PORT_16450	2
#define PORT_16550	3
#define PORT_16550A	4
#define PORT_CIRRUS     5	/* usurped by cyclades.c */
#define PORT_16650	6
#define PORT_16650V2	7
#define PORT_16750	8
#define PORT_STARTECH	9	/* usurped by cyclades.c */
#define PORT_16C950	10	/* Oxford Semiconductor */
#define PORT_16654	11
#define PORT_16850	12
#define PORT_RSA	13	/* RSA-DV II/S card */
#define PORT_MAX	13

/*********Add Dengtao Bengining 2005-09-27************/
#define HWA_CPCI_3544_PORT_NUM     4
#define HWA_CPCI_3544_BPS_MAX      13
#define HWA_CPCI_3544_SIZEOF		4
/********Add  Dengtao Ending 2005-09-27**************/



typedef struct pciBoardResource      /* PCI_BOARD_RESOURCE */
    {
    UINT32        pciBus;            /* PCI Bus number */
    UINT32        pciDevice;         /* PCI Device number */
    UINT32        pciFunc;           /* PCI Function number */

    UINT32        vendorID;          /* PCI Vendor ID */
    UINT32        deviceID;          /* PCI Device ID */
    UINT8         revisionID;        /* PCI Revision ID */
    UINT32        boardType;         /* BSP-specific board type ID */

    UINT8         irq;               /* Interrupt Request Level */
    UINT32        irqvec;            /* Interrupt Request vector */

    UINT32        bar [6];           /* PCI Base Address Registers */

    void * const  pExtended;         /* pointer to extended device info */

    } PCI_BOARD_RESOURCE;


#define PCI_OUT_BYTE(addr, data) 	sysOutByte (addr, data)
	
#define PCI_IN_BYTE(addr) 	sysInByte (addr)

/*****************dengtao Add Beginning 2005-09-27*************************/
 BOOL Hwa_COM_Install(UINT8 Com_Index, int BPS,BOOL Stop_Bit,UCHAR Odd_Enable,UCHAR Com_Size );
 int  Hwa_Com_fd[HWA_CPCI_3544_PORT_NUM];
  BOOL Hwa_CPCI_3544_Transmit(UCHAR Com_Index,char *ptr, ULONG len);  
 long Hwa_CPCI_3544_Receive(UCHAR Com_Index, UCHAR *ptr, ULONG len);
 BOOL HWA_Close_Task(UCHAR Com_Index);
/*****************dengtao Add Ending 2005-09-27*************************/
#if defined(__STDC__) || defined(__cplusplus)

extern void p3544HrdInit(p3544_CHAN *pDev);
extern void p3544Int (p3544_CHAN  *pDev);

#else

extern void p3544HrdInit();
extern void p3544Int();
	     
#endif  /* __STDC__ */

#endif	/* _ASMLANGUAGE */

#ifdef __cplusplus
}
#endif

#endif	/* __INCp3544h */