usb1_fpga.edf

USB v1.1 RTL and design specification

           (port D (direction INPUT))
           (port C (direction INPUT)
 )
         )
       )
    )
    (cell FDP (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port Q (direction OUTPUT))
           (port D (direction INPUT))
           (port C (direction INPUT)
 )
           (port PRE (direction INPUT))
         )
       )
    )
    (cell FDC (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port Q (direction OUTPUT))
           (port D (direction INPUT))
           (port C (direction INPUT)
 )
           (port CLR (direction INPUT))
         )
       )
    )
    (cell FDE (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port Q (direction OUTPUT))
           (port D (direction INPUT))
           (port C (direction INPUT)
 )
           (port CE (direction INPUT))
         )
       )
    )
    (cell FDPE (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port Q (direction OUTPUT))
           (port D (direction INPUT))
           (port C (direction INPUT)
 )
           (port PRE (direction INPUT))
           (port CE (direction INPUT))
         )
       )
    )
    (cell FDCE (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port Q (direction OUTPUT))
           (port D (direction INPUT))
           (port C (direction INPUT)
 )
           (port CLR (direction INPUT))
           (port CE (direction INPUT))
         )
       )
    )
    (cell INV (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell GND (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port G (direction OUTPUT))
         )
       )
    )
    (cell VCC (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port P (direction OUTPUT))
         )
       )
    )
  )
  (library work
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell usb1_fifo2 (cellType GENERIC)
       (view netlist (viewType NETLIST)
         (interface
           (port (array (rename tx_data_st "tx_data_st[7:0]") 8) (direction INPUT))
           (port (array (rename tx_data_st_o "tx_data_st_o[7:0]") 8) (direction OUTPUT))
           (port state_2 (direction INPUT))
           (port state_0 (direction INPUT))
           (port ff_we (direction INPUT))
           (port N_77 (direction INPUT))
           (port N_76 (direction INPUT))
           (port rst_local_i (direction INPUT))
           (port clk_i_c (direction INPUT))
         )
         (contents
          (instance rp (viewRef PRIM (cellRef FDCE (libraryRef UNILIB)))
          )
          (instance wp (viewRef PRIM (cellRef FDCE (libraryRef UNILIB)))
          )
          (instance un1_clr (viewRef PRIM (cellRef LUT4 (libraryRef VIRTEX)))
           (property init (string "FF75"))
          )
          (instance un1_clr_1 (viewRef PRIM (cellRef LUT3 (libraryRef VIRTEX)))
           (property init (string "FD"))
          )
          (instance wp_6 (viewRef PRIM (cellRef LUT3 (libraryRef VIRTEX)))
           (property init (string "02"))
          )
          (instance rp_6 (viewRef PRIM (cellRef LUT3 (libraryRef VIRTEX)))
           (property init (string "02"))
          )
          (instance (rename mem_I_8 "mem.I_8") (viewRef PRIM (cellRef RAM16X1D (libraryRef VIRTEX)))
          )
          (instance (rename mem_I_7 "mem.I_7") (viewRef PRIM (cellRef RAM16X1D (libraryRef VIRTEX)))
          )
          (instance (rename mem_I_6 "mem.I_6") (viewRef PRIM (cellRef RAM16X1D (libraryRef VIRTEX)))
          )
          (instance (rename mem_I_5 "mem.I_5") (viewRef PRIM (cellRef RAM16X1D (libraryRef VIRTEX)))
          )
          (instance (rename mem_I_4 "mem.I_4") (viewRef PRIM (cellRef RAM16X1D (libraryRef VIRTEX)))
          )
          (instance (rename mem_I_3 "mem.I_3") (viewRef PRIM (cellRef RAM16X1D (libraryRef VIRTEX)))
          )
          (instance (rename mem_I_2 "mem.I_2") (viewRef PRIM (cellRef RAM16X1D (libraryRef VIRTEX)))
          )
          (instance (rename mem_I_1 "mem.I_1") (viewRef PRIM (cellRef RAM16X1D (libraryRef VIRTEX)))
          )
          (instance GND (viewRef PRIM (cellRef GND (libraryRef UNILIB)))          )
          (net (rename tx_data_st_0 "tx_data_st[0]") (joined
           (portRef (member tx_data_st 7))
           (portRef D (instanceRef mem_I_1))
          ))
          (net (rename tx_data_st_1 "tx_data_st[1]") (joined
           (portRef (member tx_data_st 6))
           (portRef D (instanceRef mem_I_4))
          ))
          (net (rename tx_data_st_2 "tx_data_st[2]") (joined
           (portRef (member tx_data_st 5))
           (portRef D (instanceRef mem_I_3))
          ))
          (net (rename tx_data_st_3 "tx_data_st[3]") (joined
           (portRef (member tx_data_st 4))
           (portRef D (instanceRef mem_I_2))
          ))
          (net (rename tx_data_st_4 "tx_data_st[4]") (joined
           (portRef (member tx_data_st 3))
           (portRef D (instanceRef mem_I_5))
          ))
          (net (rename tx_data_st_5 "tx_data_st[5]") (joined
           (portRef (member tx_data_st 2))
           (portRef D (instanceRef mem_I_8))
          ))
          (net (rename tx_data_st_6 "tx_data_st[6]") (joined
           (portRef (member tx_data_st 1))
           (portRef D (instanceRef mem_I_7))
          ))
          (net (rename tx_data_st_7 "tx_data_st[7]") (joined
           (portRef (member tx_data_st 0))
           (portRef D (instanceRef mem_I_6))
          ))
          (net (rename tx_data_st_o_0 "tx_data_st_o[0]") (joined
           (portRef DPO (instanceRef mem_I_1))
           (portRef (member tx_data_st_o 7))
          ))
          (net (rename tx_data_st_o_1 "tx_data_st_o[1]") (joined
           (portRef DPO (instanceRef mem_I_4))
           (portRef (member tx_data_st_o 6))
          ))
          (net (rename tx_data_st_o_2 "tx_data_st_o[2]") (joined
           (portRef DPO (instanceRef mem_I_3))
           (portRef (member tx_data_st_o 5))
          ))
          (net (rename tx_data_st_o_3 "tx_data_st_o[3]") (joined
           (portRef DPO (instanceRef mem_I_2))
           (portRef (member tx_data_st_o 4))
          ))
          (net (rename tx_data_st_o_4 "tx_data_st_o[4]") (joined
           (portRef DPO (instanceRef mem_I_5))
           (portRef (member tx_data_st_o 3))
          ))
          (net (rename tx_data_st_o_5 "tx_data_st_o[5]") (joined
           (portRef DPO (instanceRef mem_I_8))
           (portRef (member tx_data_st_o 2))
          ))
          (net (rename tx_data_st_o_6 "tx_data_st_o[6]") (joined
           (portRef DPO (instanceRef mem_I_7))
           (portRef (member tx_data_st_o 1))
          ))
          (net (rename tx_data_st_o_7 "tx_data_st_o[7]") (joined
           (portRef DPO (instanceRef mem_I_6))
           (portRef (member tx_data_st_o 0))
          ))
          (net state_2 (joined
           (portRef state_2)
           (portRef I1 (instanceRef rp_6))
           (portRef I1 (instanceRef wp_6))
           (portRef I1 (instanceRef un1_clr_1))
           (portRef I3 (instanceRef un1_clr))
          ))
          (net state_0 (joined
           (portRef state_0)
           (portRef I2 (instanceRef un1_clr))
          ))
          (net ff_we (joined
           (portRef ff_we)
           (portRef WE (instanceRef mem_I_1))
           (portRef WE (instanceRef mem_I_2))
           (portRef WE (instanceRef mem_I_3))
           (portRef WE (instanceRef mem_I_4))
           (portRef WE (instanceRef mem_I_5))
           (portRef WE (instanceRef mem_I_6))
           (portRef WE (instanceRef mem_I_7))
           (portRef WE (instanceRef mem_I_8))
           (portRef I2 (instanceRef un1_clr_1))
          ))
          (net (rename n_77 "N_77") (joined
           (portRef N_77)
           (portRef I1 (instanceRef un1_clr))
          ))
          (net (rename n_76 "N_76") (joined
           (portRef N_76)
           (portRef I0 (instanceRef rp_6))
           (portRef I0 (instanceRef wp_6))
           (portRef I0 (instanceRef un1_clr_1))
           (portRef I0 (instanceRef un1_clr))
          ))
          (net rst_local_i (joined
           (portRef rst_local_i)
           (portRef CLR (instanceRef wp))
           (portRef CLR (instanceRef rp))
          ))
          (net clk_i_c (joined
           (portRef clk_i_c)
           (portRef WCLK (instanceRef mem_I_1))
           (portRef WCLK (instanceRef mem_I_2))
           (portRef WCLK (instanceRef mem_I_3))
           (portRef WCLK (instanceRef mem_I_4))
           (portRef WCLK (instanceRef mem_I_5))
           (portRef WCLK (instanceRef mem_I_6))
           (portRef WCLK (instanceRef mem_I_7))
           (portRef WCLK (instanceRef mem_I_8))
           (portRef C (instanceRef wp))
           (portRef C (instanceRef rp))
          ))
          (net (rename rpZ0 "rp") (joined
           (portRef Q (instanceRef rp))
           (portRef DPRA0 (instanceRef mem_I_1))
           (portRef DPRA0 (instanceRef mem_I_2))
           (portRef DPRA0 (instanceRef mem_I_3))
           (portRef DPRA0 (instanceRef mem_I_4))
           (portRef DPRA0 (instanceRef mem_I_5))
           (portRef DPRA0 (instanceRef mem_I_6))
           (portRef DPRA0 (instanceRef mem_I_7))
           (portRef DPRA0 (instanceRef mem_I_8))
           (portRef I2 (instanceRef rp_6))
          ))
          (net (rename rpZ0Z_6 "rp_6") (joined
           (portRef O (instanceRef rp_6))
           (portRef D (instanceRef rp))
          ))
          (net un1_clr_n (joined
           (portRef O (instanceRef un1_clr))
           (portRef CE (instanceRef rp))
          ))
          (net (rename wpZ0 "wp") (joined
           (portRef Q (instanceRef wp))
           (portRef A0 (instanceRef mem_I_1))
           (portRef A0 (instanceRef mem_I_2))
           (portRef A0 (instanceRef mem_I_3))
           (portRef A0 (instanceRef mem_I_4))
           (portRef A0 (instanceRef mem_I_5))
           (portRef A0 (instanceRef mem_I_6))
           (portRef A0 (instanceRef mem_I_7))
           (portRef A0 (instanceRef mem_I_8))
           (portRef I2 (instanceRef wp_6))
          ))
          (net (rename wpZ0Z_6 "wp_6") (joined
           (portRef O (instanceRef wp_6))
           (portRef D (instanceRef wp))
          ))
          (net un1_clr_1_n (joined
           (portRef O (instanceRef un1_clr_1))
           (portRef CE (instanceRef wp))
          ))
          (net (rename GNDZ0 "GND") (joined
           (portRef G (instanceRef GND))
           (portRef DPRA3 (instanceRef mem_I_1))
           (portRef DPRA2 (instanceRef mem_I_1))
           (portRef DPRA1 (instanceRef mem_I_1))
           (portRef A3 (instanceRef mem_I_1))
           (portRef A2 (instanceRef mem_I_1))
           (portRef A1 (instanceRef mem_I_1))
           (portRef DPRA3 (instanceRef mem_I_2))
           (portRef DPRA2 (instanceRef mem_I_2))
           (portRef DPRA1 (instanceRef mem_I_2))
           (portRef A3 (instanceRef mem_I_2))
           (portRef A2 (instanceRef mem_I_2))
           (portRef A1 (instanceRef mem_I_2))
           (portRef DPRA3 (instanceRef mem_I_3))
           (portRef DPRA2 (instanceRef mem_I_3))
           (portRef DPRA1 (instanceRef mem_I_3))
           (portRef A3 (instanceRef mem_I_3))
           (portRef A2 (instanceRef mem_I_3))
           (portRef A1 (instanceRef mem_I_3))
           (portRef DPRA3 (instanceRef mem_I_4))
           (portRef DPRA2 (instanceRef mem_I_4))
           (portRef DPRA1 (instanceRef mem_I_4))
           (portRef A3 (instanceRef mem_I_4))
           (portRef A2 (instanceRef mem_I_4))
           (portRef A1 (instanceRef mem_I_4))
           (portRef DPRA3 (instanceRef mem_I_5))
           (portRef DPRA2 (instanceRef mem_I_5))
           (portRef DPRA1 (instanceRef mem_I_5))
           (portRef A3 (instanceRef mem_I_5))
           (portRef A2 (instanceRef mem_I_5))
           (portRef A1 (instanceRef mem_I_5))
           (portRef DPRA3 (instanceRef mem_I_6))
           (portRef DPRA2 (instanceRef mem_I_6))