usb1_fpga.edf

USB v1.1 RTL and design specification

(edif usb1_fpga
  (edifVersion 2 0 0)
  (edifLevel 0)
  (keywordMap (keywordLevel 0))
  (status
    (written
      (timeStamp 2004 2 24 22 30 34)
      (author "Synplicity, Inc.")
      (program "Synplify Pro" (version "7.3.3, Build 039R"))
     )
   )
  (library VIRTEX
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           (port SPO (direction OUTPUT))
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           (port A1 (direction INPUT))
           (port A2 (direction INPUT))
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           (port D (direction INPUT))
           (port DPRA0 (direction INPUT))
           (port DPRA1 (direction INPUT))
           (port DPRA2 (direction INPUT))
           (port DPRA3 (direction INPUT))
           (port WCLK (direction INPUT)
 )
           (port WE (direction INPUT))
         )
       )
    )
    (cell RAMB4_S8 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
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           (port (array (rename addr "ADDR[8:0]") 9) (direction INPUT))
           (port (array (rename di "DI[7:0]") 8) (direction INPUT))
           (port EN (direction INPUT))
           (port CLK (direction INPUT)
 )
           (port WE (direction INPUT))
           (port RST (direction INPUT))
         )
       )
    )
    (cell SRL16 (cellType GENERIC)
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        (property INIT (integer 0))
       )
    )
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 )
           (port CE (direction INPUT))
         )
        (property INIT (integer 0))
       )
    )
    (cell IBUF (cellType GENERIC)
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       )
    )
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    )
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       (view PRIM (viewType NETLIST)
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 )
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  )
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       (view PRIM (viewType NETLIST)
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 )
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    (cell FD (cellType GENERIC)
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