usb1_fpga.sdc

USB v1.1 RTL and design specification

# Synplicity, Inc. constraint file
# F:\usb1_device\fpga_demo\usb1_device.sdc
# Written on Tue Feb 24 22:29:08 2004
# by Synplify Pro, 7.3.4      Scope Editor

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# Clocks
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define_clock            -name {clk_i}  -freq 60.000 -clockgroup default_clkgroup

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# Clock to Clock
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# Inputs/Outputs
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define_input_delay -disable      -default -improve 0.00 -route 0.00
define_output_delay -disable     -default -improve 0.00 -route 0.00
define_input_delay               {dn}  5.00 -improve 0.00 -route 0.00 -ref {clk_i:r}
define_output_delay              {dn}  5.00 -improve 0.00 -route 0.00 -ref {clk_i:r}
define_input_delay               {dp}  5.00 -improve 0.00 -route 0.00 -ref {clk_i:r}
define_output_delay              {dp}  5.00 -improve 0.00 -route 0.00 -ref {clk_i:r}
define_input_delay -disable      {rst_i} -improve 0.00 -route 0.00

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# Registers
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# Multicycle Path
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# False Path
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# Delay Path
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# Attributes
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define_attribute          {rst_i} xc_pullup {1}

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# Compile Points
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# Other Constraints
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