usb1_fpga.v

USB v1.1 RTL and design specification

/////////////////////////////////////////////////////////////////////
////                                                             ////
////  USB 1.1 function IP fpga                                   ////
////                                                             ////
////                                                             ////
////  Author: Steve Chou                                         ////
////          [e-mail]                                 ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/usb1_funct/////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2004-2004 Steve Chou                          ////
////                         www.edaking.com                     ////
////                         [e-mail]                  ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////

//  CVS Log
//
//  $Id: usb1_fpga.v,v 1.0 2004/02/10 13:31:52 Steve Chou Exp $
//
//  $Date: 2004/02/10 13:31:52 $
//  $Revision: 1.0 $
//  $Author: Steve Chou $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: usb1_fpga.v,v $
//               Revision 1.0  2004/02/10 13:31:52 Steve Chou
//
//
//
//
//
//
//
//

`include "usb1_defines.v"


module usb1_fpga(clk_i, rst_i,
		dp, dn,
		buttons,
		leds
		); 		

input clk_i;
input rst_i;
inout dp;
inout dn;
input [7 : 0] buttons;
output [7 : 0] leds;

wire tx_dp;
wire tx_dn;
wire tx_oe;
wire rx_d;
wire rx_dp;
wire rx_dn;
wire [7 : 0] buttons;

reg tx_oe_l0;
wire ep1_re;
reg ep1_empty;

	always @ ( posedge clk_i )
	begin
		tx_oe_l0	<= tx_oe;
		if (tx_oe & (!tx_oe_l0)) ep1_empty <= 1'b0;
		else if (ep1_re) ep1_empty <= 1'b1;
	end

usb1_core u0(	.clk_i(			clk_i			),
		.rst_i(			rst_i			),

		// USB Misc
		.phy_tx_mode(		1'b1			),
		.usb_rst(					),
		// USB Status
		.usb_busy(					),
		.ep_sel(					),

		// Interrupts
		.dropped_frame(					),
		.misaligned_frame(				),
		.crc16_err(					),

		// Vendor Features
		.v_set_int(					),
		.v_set_feature(					),
		.wValue(					),
		.wIndex(					),
		.vendor_data(	16'h0			),

		// USB PHY Interface
		.tx_dp(			tx_dp  		    ),
		.tx_dn(			tx_dn			),
		.tx_oe(			tx_oe			),

		.rx_d(			rx_d			),
		.rx_dp(			rx_dp			),
		.rx_dn(			rx_dn			),

		// End point 1 configuration
		.ep1_cfg(		`INT  | `IN  | 14'd064			),
		// End point 1 'OUT' FIFO i/f
		.ep1_dout(					),
		.ep1_we(					),
		.ep1_full(		1'b0			),
		// End point 1 'IN' FIFO i/f
		.ep1_din(		buttons			),
		.ep1_re(		ep1_re			),
		.ep1_empty(		ep1_empty		),
		.ep1_bf_en(		1'b0			),
		.ep1_bf_size(		7'h0			),

		// End point 2 configuration
		.ep2_cfg(		14'h00			),
		// End point 2 'OUT' FIFO i/f
		.ep2_dout(					),
		.ep2_we(					),
		.ep2_full(		1'b0			),
		// End point 2 'IN' FIFO i/f
		.ep2_din(		8'h0			),
		.ep2_re(					),
		.ep2_empty(		1'b0			),
		.ep2_bf_en(		1'b0			),
		.ep2_bf_size(		7'h0			),

		// End point 3 configuration
		.ep3_cfg(		14'h00			),
		// End point 3 'OUT' FIFO i/f
		.ep3_dout(					),
		.ep3_we(					),
		.ep3_full(		1'b0			),
		// End point 3 'IN' FIFO i/f
		.ep3_din(		8'h0			),
		.ep3_re(					),
		.ep3_empty(		1'b0			),
		.ep3_bf_en(		1'b0			),
		.ep3_bf_size(		7'h0			),

		// End point 4 configuration
		.ep4_cfg(		14'h00			),
		// End point 4 'OUT' FIFO i/f
		.ep4_dout(					),
		.ep4_we(					),
		.ep4_full(		1'b0			),
		// End point 4 'IN' FIFO i/f
		.ep4_din(		8'h0			),
		.ep4_re(					),
		.ep4_empty(		1'b0			),
		.ep4_bf_en(		1'b0			),
		.ep4_bf_size(		7'h0			),

		// End point 5 configuration
		.ep5_cfg(	14'h00		),
		// End point 5 'OUT' FIFO i/f
		.ep5_dout(					),
		.ep5_we(					),
		.ep5_full(		1'b0			),
		// End point 5 'IN' FIFO i/f
		.ep5_din(		8'h0		),
		.ep5_re(				),
		.ep5_empty(		1'b0		),
		.ep5_bf_en(		1'b0			),
		.ep5_bf_size(		7'h0			),

		// End point 6 configuration
		.ep6_cfg(		14'h00			),
		// End point 6 'OUT' FIFO i/f
		.ep6_dout(					),
		.ep6_we(					),
		.ep6_full(		1'b0			),
		// End point 6 'IN' FIFO i/f
		.ep6_din(		8'h0			),
		.ep6_re(					),
		.ep6_empty(		1'b0			),
		.ep6_bf_en(		1'b0			),
		.ep6_bf_size(		7'h0			),

		// End point 7 configuration
		.ep7_cfg(		14'h00			),
		// End point 7 'OUT' FIFO i/f
		.ep7_dout(					),
		.ep7_we(					),
		.ep7_full(		1'b0			),
		// End point 7 'IN' FIFO i/f
		.ep7_din(		8'h0			),
		.ep7_re(					),
		.ep7_empty(		1'b0			),
		.ep7_bf_en(		1'b0			),
		.ep7_bf_size(		7'h0			),
		.report_data(		leds			)
		); 	

usb1_transceiver u1 (
		.dp			(dp),
		.dn			(dn),
		.tx_dp		(tx_dp),
		.tx_dn		(tx_dn),
		.tx_oe		(tx_oe),
		.rx_d		(rx_d),
		.rx_dp		(rx_dp),
		.rx_dn		(rx_dn));

endmodule