osd_top.ucf

TI evm642的源码,给那些没有买TI的评估板,却想要评估板程序的人.

INST "DDR_MODULE/DDR7/LRR_MODULE" LOC = "CLB_R12C47.S0";
INST "DDR_MODULE/DDR7/LRR_MODULE" LOC = "CLB_R12C47.S0";
#INST "DDR_MODULE/DDR7/DDROUT_MODULE/ff_crr" LOC = "CLB_R12C48.S1";
#INST "DDR_MODULE/DDR7/DDROUT_MODULE/ff_crf" LOC = "CLB_R12C48.S0";
#INST "DDR_MODULE/DDR7/DDROUT_MODULE/din_rise" LOC = "CLB_R12C48.S1";
#INST "DDR_MODULE/DDR7/DDROUT_MODULE/din_fall" LOC = "CLB_R12C48.S0";
#INST "DDR_MODULE/DDR7/DDROUT_MODULE/one_lut" LOC = "CLB_R12C48.S1"  ;
#NET "DDR_MODULE/DDR7/DDROUT_MODULE/ff_crr" MAXDELAY=600ps;
#NET "DDR_MODULE/DDR7/DDROUT_MODULE/ff_crf" MAXDELAY=600ps;
INST "DDR_MODULE/DDR7/LRF_MODULE" TNM = "FASTLATCH";
INST "DDR_MODULE/DDR7/LRR_MODULE" TNM = "FASTLATCH";
INST "DDR_MODULE/DDR6/DDROUT_MODULE" LOC = "CLB_R8C48.S0";
INST "DDR_MODULE/DDR6/LRR_MODULE" LOC = "CLB_R8C47.S0";
INST "DDR_MODULE/DDR6/LRR_MODULE" LOC = "CLB_R8C47.S0";
#INST "DDR_MODULE/DDR6/DDROUT_MODULE/ff_crr" LOC = "CLB_R8C48.S1";
#INST "DDR_MODULE/DDR6/DDROUT_MODULE/ff_crf" LOC = "CLB_R8C48.S0";
#INST "DDR_MODULE/DDR6/DDROUT_MODULE/din_rise" LOC = "CLB_R8C48.S1";
#INST "DDR_MODULE/DDR6/DDROUT_MODULE/din_fall" LOC = "CLB_R8C48.S0";
#INST "DDR_MODULE/DDR6/DDROUT_MODULE/one_lut" LOC = "CLB_R8C48.S1"  ;
#NET "DDR_MODULE/DDR6/DDROUT_MODULE/ff_crr" MAXDELAY=600ps;
#NET "DDR_MODULE/DDR6/DDROUT_MODULE/ff_crf" MAXDELAY=600ps;
INST "DDR_MODULE/DDR6/LRF_MODULE" TNM = "FASTLATCH";
INST "DDR_MODULE/DDR6/LRR_MODULE" TNM = "FASTLATCH";
INST "DDR_MODULE/DDR5/DDROUT_MODULE" LOC = "CLB_R7C48.S0";
INST "DDR_MODULE/DDR5/LRR_MODULE" LOC = "CLB_R7C47.S0";
INST "DDR_MODULE/DDR5/LRR_MODULE" LOC = "CLB_R7C47.S0";
#INST "DDR_MODULE/DDR5/DDROUT_MODULE/ff_crr" LOC = "CLB_R7C48.S1";
#INST "DDR_MODULE/DDR5/DDROUT_MODULE/ff_crf" LOC = "CLB_R7C48.S0";
#INST "DDR_MODULE/DDR5/DDROUT_MODULE/din_rise" LOC = "CLB_R7C48.S1";
#INST "DDR_MODULE/DDR5/DDROUT_MODULE/din_fall" LOC = "CLB_R7C48.S0";
#INST "DDR_MODULE/DDR5/DDROUT_MODULE/one_lut" LOC = "CLB_R7C48.S1"  ;
#NET "DDR_MODULE/DDR5/DDROUT_MODULE/ff_crr" MAXDELAY=600ps;
#NET "DDR_MODULE/DDR5/DDROUT_MODULE/ff_crf" MAXDELAY=600ps;
INST "DDR_MODULE/DDR5/LRF_MODULE" TNM = "FASTLATCH";
INST "DDR_MODULE/DDR5/LRR_MODULE" TNM = "FASTLATCH";
#INST "DDR_MODULE/DDR4/DDROUT_MODULE" LOC = "CLB_R6C48.S0";
#INST "DDR_MODULE/DDR4/DDROUT_MODULE/ff_crr" LOC = "CLB_R6C48.S1";
#INST "DDR_MODULE/DDR4/DDROUT_MODULE/ff_crf" LOC = "CLB_R6C48.S0";
#INST "DDR_MODULE/DDR4/DDROUT_MODULE/din_rise" LOC = "CLB_R6C48.S1";
#INST "DDR_MODULE/DDR4/DDROUT_MODULE/din_fall" LOC = "CLB_R6C48.S0";
#INST "DDR_MODULE/DDR4/DDROUT_MODULE/one_lut" LOC = "CLB_R6C48.S1"  ;
#INST "DDR_MODULE/DDR4/DDROUT_MODULE" LOC = "CLB_R6C48.S0";
#INST "DDR_MODULE/DDR4/LRR_MODULE" LOC = "CLB_R6C47.S0";
#INST "DDR_MODULE/DDR4/LRR_MODULE" LOC = "CLB_R6C47.S0";
INST "DDR_MODULE/DDR4/DDROUT_MODULE" LOC = "CLB_R9C48.S0";
INST "DDR_MODULE/DDR4/LRR_MODULE" LOC = "CLB_R9C47.S0";
INST "DDR_MODULE/DDR4/LRR_MODULE" LOC = "CLB_R9C47.S0";
#INST "DDR_MODULE/DDR4/DDROUT_MODULE/ff_crr" LOC = "CLB_R9C48.S1";
#INST "DDR_MODULE/DDR4/DDROUT_MODULE/ff_crf" LOC = "CLB_R9C48.S0";
#INST "DDR_MODULE/DDR4/DDROUT_MODULE/din_rise" LOC = "CLB_R9C48.S1";
#INST "DDR_MODULE/DDR4/DDROUT_MODULE/din_fall" LOC = "CLB_R9C48.S0";
#INST "DDR_MODULE/DDR4/DDROUT_MODULE/one_lut" LOC = "CLB_R9C48.S1"  ;
#NET "DDR_MODULE/DDR4/DDROUT_MODULE/ff_crr" MAXDELAY=600ps;
#NET "DDR_MODULE/DDR4/DDROUT_MODULE/ff_crf" MAXDELAY=600ps;
INST "DDR_MODULE/DDR4/LRF_MODULE" TNM = "FASTLATCH";
INST "DDR_MODULE/DDR4/LRR_MODULE" TNM = "FASTLATCH";
INST "DDR_MODULE/DDR3/DDROUT_MODULE" LOC = "CLB_R5C48.S0";
INST "DDR_MODULE/DDR3/LRR_MODULE" LOC = "CLB_R5C47.S0";
INST "DDR_MODULE/DDR3/LRR_MODULE" LOC = "CLB_R5C47.S0";
#INST "DDR_MODULE/DDR3/DDROUT_MODULE/ff_crr" LOC = "CLB_R5C48.S1";
#INST "DDR_MODULE/DDR3/DDROUT_MODULE/ff_crf" LOC = "CLB_R5C48.S0";
#INST "DDR_MODULE/DDR3/DDROUT_MODULE/din_rise" LOC = "CLB_R5C48.S1";
#INST "DDR_MODULE/DDR3/DDROUT_MODULE/din_fall" LOC = "CLB_R5C48.S0";
#INST "DDR_MODULE/DDR3/DDROUT_MODULE/one_lut" LOC = "CLB_R5C48.S1"  ;
#NET "DDR_MODULE/DDR3/DDROUT_MODULE/ff_crr" MAXDELAY=600ps;
#NET "DDR_MODULE/DDR3/DDROUT_MODULE/ff_crf" MAXDELAY=600ps;
INST "DDR_MODULE/DDR3/LRF_MODULE" TNM = "FASTLATCH";
INST "DDR_MODULE/DDR3/LRR_MODULE" TNM = "FASTLATCH";
INST "DDR_MODULE/DDR2/DDROUT_MODULE" LOC = "CLB_R4C48.S0";
INST "DDR_MODULE/DDR2/LRR_MODULE" LOC = "CLB_R4C47.S0";
INST "DDR_MODULE/DDR2/LRR_MODULE" LOC = "CLB_R4C47.S0";
#INST "DDR_MODULE/DDR2/DDROUT_MODULE/ff_crr" LOC = "CLB_R4C48.S1";
#INST "DDR_MODULE/DDR2/DDROUT_MODULE/ff_crf" LOC = "CLB_R4C48.S0";
#INST "DDR_MODULE/DDR2/DDROUT_MODULE/din_rise" LOC = "CLB_R4C48.S1";
#INST "DDR_MODULE/DDR2/DDROUT_MODULE/din_fall" LOC = "CLB_R4C48.S0";
#INST "DDR_MODULE/DDR2/DDROUT_MODULE/one_lut" LOC = "CLB_R4C48.S1"  ;
#NET "DDR_MODULE/DDR2/DDROUT_MODULE/ff_crr" MAXDELAY=600ps;
#NET "DDR_MODULE/DDR2/DDROUT_MODULE/ff_crf" MAXDELAY=600ps;
INST "DDR_MODULE/DDR2/LRF_MODULE" TNM = "FASTLATCH";
INST "DDR_MODULE/DDR2/LRR_MODULE" TNM = "FASTLATCH";
INST "DDR_MODULE/DDR1/DDROUT_MODULE" LOC = "CLB_R3C48.S0";
INST "DDR_MODULE/DDR1/LRR_MODULE" LOC = "CLB_R3C47.S0";
INST "DDR_MODULE/DDR1/LRR_MODULE" LOC = "CLB_R3C47.S0";
#INST "DDR_MODULE/DDR1/DDROUT_MODULE/ff_crr" LOC = "CLB_R3C48.S1";
#INST "DDR_MODULE/DDR1/DDROUT_MODULE/ff_crf" LOC = "CLB_R3C48.S0";
#INST "DDR_MODULE/DDR1/DDROUT_MODULE/din_rise" LOC = "CLB_R3C48.S1";
#INST "DDR_MODULE/DDR1/DDROUT_MODULE/din_fall" LOC = "CLB_R3C48.S0";
#INST "DDR_MODULE/DDR1/DDROUT_MODULE/one_lut" LOC = "CLB_R3C48.S1"  ;
#NET "DDR_MODULE/DDR1/DDROUT_MODULE/ff_crr" MAXDELAY=600ps;
#NET "DDR_MODULE/DDR1/DDROUT_MODULE/ff_crf" MAXDELAY=600ps;
INST "DDR_MODULE/DDR1/LRF_MODULE" TNM = "FASTLATCH";
INST "DDR_MODULE/DDR1/LRR_MODULE" TNM = "FASTLATCH";
#INST "DDR_MODULE/DDR0/DDROUT_MODULE" LOC = "CLB_R2C48.S0";
#INST "DDR_MODULE/DDR0/DDROUT_MODULE/ff_crr" LOC = "CLB_R2C48.S1";
#INST "DDR_MODULE/DDR0/DDROUT_MODULE/ff_crf" LOC = "CLB_R2C48.S0";
#INST "DDR_MODULE/DDR0/DDROUT_MODULE/din_rise" LOC = "CLB_R2C48.S1";
#INST "DDR_MODULE/DDR0/DDROUT_MODULE/din_fall" LOC = "CLB_R2C48.S0";
#INST "DDR_MODULE/DDR0/DDROUT_MODULE/one_lut" LOC = "CLB_R2C48.S1"  ;
INST "DDR_MODULE/DDR0/DDROUT_MODULE" LOC = "CLB_R1C48.S0";
INST "DDR_MODULE/DDR0/LRR_MODULE" LOC = "CLB_R2C48.S0";
INST "DDR_MODULE/DDR0/LRR_MODULE" LOC = "CLB_R2C48.S0";
#INST "DDR_MODULE/DDR0/DDROUT_MODULE/ff_crr" LOC = "CLB_R1C48.S1";
#INST "DDR_MODULE/DDR0/DDROUT_MODULE/ff_crf" LOC = "CLB_R1C48.S0";
#INST "DDR_MODULE/DDR0/DDROUT_MODULE/din_rise" LOC = "CLB_R1C48.S1";
#INST "DDR_MODULE/DDR0/DDROUT_MODULE/din_fall" LOC = "CLB_R1C48.S0";
#INST "DDR_MODULE/DDR0/DDROUT_MODULE/one_lut" LOC = "CLB_R1C48.S1"  ;
#NET "DDR_MODULE/DDR0/DDROUT_MODULE/ff_crr" MAXDELAY=600ps;
#NET "DDR_MODULE/DDR0/DDROUT_MODULE/ff_crf" MAXDELAY=600ps;
INST "DDR_MODULE/DDR0/LRF_MODULE" TNM = "FASTLATCH";
INST "DDR_MODULE/DDR0/LRR_MODULE" TNM = "FASTLATCH";
#INST "DDR_MODULE/DDRCLK/DDROUT_MODULE" LOC = "CLB_R1C48.S0";
#INST "DDR_MODULE/DDRCLK/DDROUT_MODULE/ff_crr" LOC = "CLB_R1C48.S1";
#INST "DDR_MODULE/DDRCLK/DDROUT_MODULE/ff_crf" LOC = "CLB_R1C48.S0";
#INST "DDR_MODULE/DDRCLK/DDROUT_MODULE/din_rise" LOC = "CLB_R1C48.S1";
#INST "DDR_MODULE/DDRCLK/DDROUT_MODULE/din_fall" LOC = "CLB_R1C48.S0";
#INST "DDR_MODULE/DDRCLK/DDROUT_MODULE/one_lut" LOC = "CLB_R1C48.S1"  ;
INST "DDR_MODULE/DDRCLK/DDROUT_MODULE" LOC = "CLB_R1C47.S0";
INST "DDR_MODULE/DDRCLK/LRR_MODULE" LOC = "CLB_R2C47.S0";
INST "DDR_MODULE/DDRCLK/LRR_MODULE" LOC = "CLB_R2C47.S0";
#INST "DDR_MODULE/DDRCLK/DDROUT_MODULE/ff_crr" LOC = "CLB_R1C47.S1";
#INST "DDR_MODULE/DDRCLK/DDROUT_MODULE/ff_crf" LOC = "CLB_R1C47.S0";
#INST "DDR_MODULE/DDRCLK/DDROUT_MODULE/din_rise" LOC = "CLB_R1C47.S1";
#INST "DDR_MODULE/DDRCLK/DDROUT_MODULE/din_fall" LOC = "CLB_R1C47.S0";
#INST "DDR_MODULE/DDRCLK/DDROUT_MODULE/one_lut" LOC = "CLB_R1C47.S1"  ;
#NET "DDR_MODULE/DDRCLK/DDROUT_MODULE/ff_crr" MAXDELAY=600ps;
#NET "DDR_MODULE/DDRCLK/DDROUT_MODULE/ff_crf" MAXDELAY=600ps;
INST "DDR_MODULE/DDRCLK/LRF_MODULE" TNM = "FASTLATCH";
INST "DDR_MODULE/DDRCLK/LRR_MODULE" TNM = "FASTLATCH";
INST "ED(0)" TNM = "EDATA";
INST "ED(1)" TNM = "EDATA";
INST "ED(2)" TNM = "EDATA";
INST "ED(3)" TNM = "EDATA";
INST "ED(4)" TNM = "EDATA";
INST "ED(5)" TNM = "EDATA";
INST "ED(6)" TNM = "EDATA";
INST "ED(7)" TNM = "EDATA";
INST "ED(8)" TNM = "EDATA";
INST "ED(9)" TNM = "EDATA";
INST "ED(10)" TNM = "EDATA";
INST "ED(11)" TNM = "EDATA";
INST "ED(12)" TNM = "EDATA";
INST "ED(13)" TNM = "EDATA";
INST "ED(14)" TNM = "EDATA";
INST "ED(15)" TNM = "EDATA";
INST "ED(16)" TNM = "EDATA";
INST "ED(17)" TNM = "EDATA";
INST "ED(18)" TNM = "EDATA";
INST "ED(19)" TNM = "EDATA";
INST "ED(20)" TNM = "EDATA";
INST "ED(21)" TNM = "EDATA";
INST "ED(22)" TNM = "EDATA";
INST "ED(23)" TNM = "EDATA";
INST "ED(24)" TNM = "EDATA";
INST "ED(25)" TNM = "EDATA";
INST "ED(26)" TNM = "EDATA";
INST "ED(27)" TNM = "EDATA";
INST "ED(28)" TNM = "EDATA";
INST "ED(29)" TNM = "EDATA";
INST "ED(30)" TNM = "EDATA";
INST "ED(31)" TNM = "EDATA";
#TIMEGRP "EDATA" OFFSET = OUT 15 ns AFTER "EMIF_CLK";
NET "DENCDATA(0)" FAST;
NET "DENCDATA(1)" FAST;
NET "DENCDATA(2)" FAST;
NET "DENCDATA(3)" FAST;
NET "DENCDATA(4)" FAST;
NET "DENCDATA(5)" FAST;
NET "DENCDATA(6)" FAST;
NET "DENCDATA(7)" FAST;
NET "DENCDATA(0)" DRIVE = 4;
NET "DENCDATA(1)" DRIVE = 4;
NET "DENCDATA(2)" DRIVE = 4;
NET "DENCDATA(3)" DRIVE = 4;
NET "DENCDATA(4)" DRIVE = 4;
NET "DENCDATA(5)" DRIVE = 4;
NET "DENCDATA(6)" DRIVE = 4;
NET "DENCDATA(7)" DRIVE = 4;
NET "PIXCLKI" FAST;
NET "PIXCLKI" DRIVE = 8;
NET "VP2CLK1" TNM_NET = "VP2CLK1";
TIMESPEC "TS_VP2CLK1" = PERIOD "VP2CLK1" 80 MHz HIGH 50 %;
#TIMESPEC "TS_P2P" = FROM "PADS" TO "PADS" 2 ns;
NET "VP2D(12)" IOBDELAY = BOTH;
NET "VP2D(13)" IOBDELAY = BOTH;
NET "VP2D(9)" IOBDELAY = BOTH;
NET "VP2D(8)" IOBDELAY = BOTH;
NET "VP2D(7)" IOBDELAY = BOTH;
NET "VP2D(6)" IOBDELAY = BOTH;
NET "VP2D(14)" IOBDELAY = BOTH;
NET "VP2D(5)" IOBDELAY = BOTH;
NET "VP2D(2)" IOBDELAY = BOTH;
NET "VP2D(3)" IOBDELAY = BOTH;
NET "VP2D(4)" IOBDELAY = BOTH;
NET "VP2D(15)" IOBDELAY = BOTH;
NET "VP2D(16)" IOBDELAY = BOTH;
NET "VP2D(17)" IOBDELAY = BOTH;
NET "VP2D(18)" IOBDELAY = BOTH;
NET "VP2D(19)" IOBDELAY = BOTH;
NET "VP2CTL0" IOBDELAY = BOTH;
NET "VP2CTL1" IOBDELAY = BOTH;
NET "VP2CTL2" IOBDELAY = BOTH;
INST "DDR_MODULE/dencdata_falling[0]" TNM = "ddr_input";
INST "DDR_MODULE/dencdata_falling[1]" TNM = "ddr_input";
INST "DDR_MODULE/dencdata_falling[2]" TNM = "ddr_input";
INST "DDR_MODULE/dencdata_falling[3]" TNM = "ddr_input";
INST "DDR_MODULE/dencdata_falling[4]" TNM = "ddr_input";
INST "DDR_MODULE/dencdata_falling[5]" TNM = "ddr_input";
INST "DDR_MODULE/dencdata_falling[6]" TNM = "ddr_input";
INST "DDR_MODULE/dencdata_falling[7]" TNM = "ddr_input";
INST "DDR_MODULE/dencdata_rising[0]" TNM = "ddr_input";
INST "DDR_MODULE/dencdata_rising[1]" TNM = "ddr_input";
INST "DDR_MODULE/dencdata_rising[2]" TNM = "ddr_input";
INST "DDR_MODULE/dencdata_rising[3]" TNM = "ddr_input";
INST "DDR_MODULE/dencdata_rising[4]" TNM = "ddr_input";
INST "DDR_MODULE/dencdata_rising[5]" TNM = "ddr_input";
INST "DDR_MODULE/dencdata_rising[6]" TNM = "ddr_input";
INST "DDR_MODULE/dencdata_rising[7]" TNM = "ddr_input";
INST "DENCDATA(0)" TNM = "ddr_output";
INST "DENCDATA(1)" TNM = "ddr_output";
INST "DENCDATA(2)" TNM = "ddr_output";
INST "DENCDATA(3)" TNM = "ddr_output";
INST "DENCDATA(4)" TNM = "ddr_output";
INST "DENCDATA(5)" TNM = "ddr_output";
INST "DENCDATA(6)" TNM = "ddr_output";
INST "DENCDATA(7)" TNM = "ddr_output";
TIMESPEC "TS_DDR" = FROM "ddr_input" TO "ddr_output" 2 ns;