osd_top.ucf

TI evm642的源码,给那些没有买TI的评估板,却想要评估板程序的人.

NET "EMIF_CLK" TNM_NET = "EMIF_CLK";
TIMESPEC "TS_EMIF_CLK" = PERIOD "EMIF_CLK" 133 MHz HIGH 50 %;
#NET "PIXCLKO" TNM_NET = "PIXCLKO";
#TIMESPEC "TS_PIXCLKO" = PERIOD "PIXCLKO" 80 MHz HIGH 50 %;
NET "AAOEz" OFFSET = IN 2 ns BEFORE "EMIF_CLK";
NET "AAREz" OFFSET = IN 2 ns BEFORE "EMIF_CLK";
NET "AAWEz" OFFSET = IN 2 ns BEFORE "EMIF_CLK";
NET "CE1z" OFFSET = IN 2 ns BEFORE "EMIF_CLK";
NET "CE2z" OFFSET = IN 2 ns BEFORE "EMIF_CLK";
NET "CE3z" OFFSET = IN 2 ns BEFORE "EMIF_CLK";
NET "DC_EMIF_DIR" OFFSET = OUT 2 ns AFTER "EMIF_CLK";
NET "DC_EMIF_OEz" OFFSET = OUT 2 ns AFTER "EMIF_CLK";
NET "DENCDATA_c(0)" MAXDELAY = 4 ns;
NET "DENCDATA_c(1)" MAXDELAY = 4 ns;
NET "DENCDATA_c(2)" MAXDELAY = 4 ns;
NET "DENCDATA_c(3)" MAXDELAY = 4 ns;
NET "DENCDATA_c(4)" MAXDELAY = 4 ns;
NET "DENCDATA_c(5)" MAXDELAY = 4 ns;
NET "DENCDATA_c(6)" MAXDELAY = 4 ns;
NET "DENCDATA_c(7)" MAXDELAY = 4 ns;
NET "PIXCLKI_C" MAXDELAY = 4 ns;
#NET "VP2CLK0_C" MAXDELAY = 2 ns;
NET "DENC_HSYNC" OFFSET = OUT 9 ns AFTER "VP2CLK1";
NET "DENC_VSYNC" OFFSET = OUT 9 ns AFTER "VP2CLK1";
NET "EA(3)" OFFSET = IN 2 ns BEFORE "EMIF_CLK";
NET "EA(4)" OFFSET = IN 2 ns BEFORE "EMIF_CLK";
NET "EA(5)" OFFSET = IN 2 ns BEFORE "EMIF_CLK";
NET "EA(6)" OFFSET = IN 2 ns BEFORE "EMIF_CLK";
NET "EA(7)" OFFSET = IN 2 ns BEFORE "EMIF_CLK";
NET "EA_22" OFFSET = IN 2 ns BEFORE "EMIF_CLK";
NET "ED(0)" OFFSET = IN 2 ns BEFORE "EMIF_CLK";
NET "ED(1)" OFFSET = IN 2 ns BEFORE "EMIF_CLK";
NET "ED(2)" OFFSET = IN 2 ns BEFORE "EMIF_CLK";
NET "ED(3)" OFFSET = IN 2 ns BEFORE "EMIF_CLK";
NET "ED(4)" OFFSET = IN 2 ns BEFORE "EMIF_CLK";
NET "ED(5)" OFFSET = IN 2 ns BEFORE "EMIF_CLK";
NET "ED(6)" OFFSET = IN 2 ns BEFORE "EMIF_CLK";
NET "ED(7)" OFFSET = IN 2 ns BEFORE "EMIF_CLK";
NET "ED(8)" OFFSET = IN 2 ns BEFORE "EMIF_CLK";
NET "ED(9)" OFFSET = IN 2 ns BEFORE "EMIF_CLK";
NET "ED(10)" OFFSET = IN 2 ns BEFORE "EMIF_CLK";
NET "ED(11)" OFFSET = IN 2 ns BEFORE "EMIF_CLK";
NET "ED(12)" OFFSET = IN 2 ns BEFORE "EMIF_CLK";
NET "ED(13)" OFFSET = IN 2 ns BEFORE "EMIF_CLK";
NET "ED(14)" OFFSET = IN 2 ns BEFORE "EMIF_CLK";
NET "ED(15)" OFFSET = IN 2 ns BEFORE "EMIF_CLK";
NET "ED(16)" OFFSET = IN 2 ns BEFORE "EMIF_CLK";
NET "ED(17)" OFFSET = IN 2 ns BEFORE "EMIF_CLK";
NET "ED(18)" OFFSET = IN 2 ns BEFORE "EMIF_CLK";
NET "ED(19)" OFFSET = IN 2 ns BEFORE "EMIF_CLK";
NET "ED(20)" OFFSET = IN 2 ns BEFORE "EMIF_CLK";
NET "ED(21)" OFFSET = IN 2 ns BEFORE "EMIF_CLK";
NET "ED(22)" OFFSET = IN 2 ns BEFORE "EMIF_CLK";
NET "ED(23)" OFFSET = IN 2 ns BEFORE "EMIF_CLK";
NET "ED(24)" OFFSET = IN 2 ns BEFORE "EMIF_CLK";
NET "ED(25)" OFFSET = IN 2 ns BEFORE "EMIF_CLK";
NET "ED(26)" OFFSET = IN 2 ns BEFORE "EMIF_CLK";
NET "ED(27)" OFFSET = IN 2 ns BEFORE "EMIF_CLK";
NET "ED(28)" OFFSET = IN 2 ns BEFORE "EMIF_CLK";
NET "ED(29)" OFFSET = IN 2 ns BEFORE "EMIF_CLK";
NET "ED(30)" OFFSET = IN 2 ns BEFORE "EMIF_CLK";
NET "ED(31)" OFFSET = IN 2 ns BEFORE "EMIF_CLK";
NET "VP2CTL1" OFFSET = IN 3 ns BEFORE "VP2CLK1";
NET "VP2CTL2" OFFSET = IN 3 ns BEFORE "VP2CLK1";
NET "VP2CTL0" OFFSET = IN 3 ns BEFORE "VP2CLK1";
INST "VP2D(2)" TNM = "VDATA";
INST "VP2D(3)" TNM = "VDATA";
INST "VP2D(4)" TNM = "VDATA";
INST "VP2D(5)" TNM = "VDATA";
INST "VP2D(6)" TNM = "VDATA";
INST "VP2D(7)" TNM = "VDATA";
INST "VP2D(8)" TNM = "VDATA";
INST "VP2D(9)" TNM = "VDATA";
INST "VP2D(12)" TNM = "VDATA";
INST "VP2D(13)" TNM = "VDATA";
INST "VP2D(14)" TNM = "VDATA";
INST "VP2D(15)" TNM = "VDATA";
INST "VP2D(16)" TNM = "VDATA";
INST "VP2D(17)" TNM = "VDATA";
INST "VP2D(18)" TNM = "VDATA";
INST "VP2D(19)" TNM = "VDATA";
TIMEGRP "VDATA" OFFSET = IN 3 ns BEFORE "VP2CLK1";
# Start of Constraints extracted by Floorplanner from the Design
NET "DENC_HSYNC" DRIVE = 8;
NET "DENC_VSYNC" DRIVE = 8;
NET "DENC_HSYNC" FAST;
NET "DENC_VSYNC" FAST;
#PACE: Start of Constraints extracted by PACE from the Design
NET "VP2D(19)" LOC = "P100";
NET "VP2D(18)" LOC = "P101";
NET "VP2D(17)" LOC = "P108";
NET "VP2D(16)" LOC = "P109";
NET "VP2D(15)" LOC = "P110";
NET "VP2D(14)" LOC = "P111";
NET "VP2D(13)" LOC = "P112";
NET "VP2D(12)" LOC = "P113";
NET "VP2D(11)" LOC = "P96";
NET "VP2D(10)" LOC = "P97";
NET "VP2D(9)" LOC = "P120";
NET "VP2D(8)" LOC = "P121";
NET "VP2D(7)" LOC = "P122";
NET "VP2D(6)" LOC = "P123";
NET "VP2D(5)" LOC = "P125";
NET "VP2D(4)" LOC = "P126";
NET "VP2D(3)" LOC = "P127";
NET "VP2D(2)" LOC = "P129";
NET "VP2D(1)" LOC = "P98";
NET "VP2D(0)" LOC = "P99";
NET "VP2CTL2" LOC = "P116";
NET "VP2CTL1" LOC = "P115";
NET "VP2CTL0" LOC = "P114";
NET "VP2CLK1" LOC = "P80";
NET "VP2CLK0" LOC = "P102";
NET "UART_INTB" LOC = "P193";
NET "UART_INTA" LOC = "P194";
#NET "UART_CSz(1)" LOC = "P191";
#NET "UART_CSz(0)" LOC = "P192";
NET "UART_TXRDYB" LOC = "P81";
NET "UART_TXRDYA" LOC = "P82";
NET "UART_RXRDYB" LOC = "P83";
NET "UART_RXRDYA" LOC = "P84";
NET "TVDETECT" LOC = "P132";
NET "RTS0_B" LOC = "P198";
NET "RTS0_A" LOC = "P199";
NET "RESETz" LOC = "P180";
NET "PLL_MS" LOC = "P75";
NET "PLL_MD" LOC = "P62";
NET "PLL_MC" LOC = "P61";
NET "PIXCLKO" LOC = "P182";
NET "PIXCLKI" LOC = "P160";
#NET "MON_VSYNC" LOC = "P179";
#NET "MON_HSYNC" LOC = "P178";
NET "LED(7)" LOC = "P74";
NET "LED(6)" LOC = "P73";
NET "LED(5)" LOC = "P71";
NET "LED(4)" LOC = "P70";
NET "LED(3)" LOC = "P69";
NET "LED(2)" LOC = "P68";
NET "LED(1)" LOC = "P64";
NET "LED(0)" LOC = "P63";
NET "GPIO(7)" LOC = "P162";
NET "GPIO(6)" LOC = "P163";
NET "GPIO(5)" LOC = "P164";
NET "GPIO(4)" LOC = "P165";
NET "GPIO(3)" LOC = "P166";
NET "GPIO(2)" LOC = "P167";
NET "GPIO(1)" LOC = "P168";
NET "GPIO(0)" LOC = "P169";
NET "FLASH_PAGEz(2)" LOC = "P187";
NET "FLASH_PAGEz(1)" LOC = "P188";
NET "FLASH_PAGEz(0)" LOC = "P189";
NET "EMIF_CLK" LOC = "P77";
NET "EINT7" LOC = "P200";
NET "EINT6" LOC = "P107";
NET "ED(31)" LOC = "P58";
NET "ED(30)" LOC = "P57";
NET "ED(29)" LOC = "P56";
NET "ED(28)" LOC = "P55";
NET "ED(27)" LOC = "P49";
NET "ED(26)" LOC = "P48";
NET "ED(25)" LOC = "P47";
NET "ED(24)" LOC = "P46";
NET "ED(23)" LOC = "P45";
NET "ED(22)" LOC = "P44";
NET "ED(21)" LOC = "P43";
NET "ED(20)" LOC = "P42";
NET "ED(19)" LOC = "P41";
NET "ED(18)" LOC = "P40";
NET "ED(17)" LOC = "P36";
NET "ED(16)" LOC = "P35";
NET "ED(15)" LOC = "P17";
NET "ED(14)" LOC = "P16";
NET "ED(13)" LOC = "P15";
NET "ED(12)" LOC = "P11";
NET "ED(11)" LOC = "P10";
NET "ED(10)" LOC = "P9";
NET "ED(9)" LOC = "P8";
NET "ED(8)" LOC = "P7";
NET "ED(7)" LOC = "P6";
NET "ED(6)" LOC = "P5";
NET "ED(5)" LOC = "P4";
NET "ED(4)" LOC = "P3";
NET "ED(3)" LOC = "P206";
NET "ED(2)" LOC = "P205";
NET "ED(1)" LOC = "P204";
NET "ED(0)" LOC = "P203";
NET "EA_22" LOC = "P24";
NET "EA(7)" LOC = "P23";
NET "EA(6)" LOC = "P22";
NET "EA(5)" LOC = "P21";
NET "EA(4)" LOC = "P20";
NET "EA(3)" LOC = "P18";
NET "DENC_VSYNC" LOC = "P146";
NET "DENC_VSYNC" IOSTANDARD = LVTTL;
#NET "DENC_VSM" LOC = "P176";
NET "DENC_HSYNC" LOC = "P145";
NET "DENC_HSYNC" IOSTANDARD = LVTTL;
#NET "DENC_FIELD" LOC = "P141";
NET "DENC_FIELD" LOC = "P149";
#NET "DENC_CSYNC" LOC = "P140";
#NET "DENC_BLANK" LOC = "P133";
NET "DENCDATA(11)" LOC = "P134";
NET "DENCDATA(10)" LOC = "P135";
NET "DENCDATA(9)" LOC = "P136";
NET "DENCDATA(8)" LOC = "P138";
NET "DENCDATA(7)" LOC = "P139";
NET "DENCDATA(6)" LOC = "P147";
NET "DENCDATA(5)" LOC = "P148";
#NET "DENCDATA(4)" LOC = "P149";
NET "DENCDATA(4)" LOC = "P141";
NET "DENCDATA(3)" LOC = "P150";
NET "DENCDATA(2)" LOC = "P151";
NET "DENCDATA(1)" LOC = "P152";
NET "DENCDATA(0)" LOC = "P154";
NET "DC_EMIF_OEz" LOC = "P59";
NET "DC_EMIF_DIR" LOC = "P60";
NET "CE3z" LOC = "P34";
NET "CE2z" LOC = "P33";
NET "CE1z" LOC = "P31";
NET "ASOE3z" LOC = "P202";
NET "AAWEz" LOC = "P29";
NET "AAREz" LOC = "P27";
NET "AAOEz" LOC = "P30";
#AREA_GROUP "AG_EMIF_IF_MODULE" RANGE = CLB_R3C1:CLB_R7C6 ;
#INST EMIF_IF_MODULE AREA_GROUP = AG_EMIF_IF_MODULE ;
#AREA_GROUP "AG_SYNC_REG_MODULE" RANGE = CLB_R3C7:CLB_R7C15 ;
#INST SYNC_REG_MODULE AREA_GROUP = AG_SYNC_REG_MODULE ;
INST "DDR_MODULE/DDR7/DDROUT_MODULE" LOC = "CLB_R12C48.S0";