fifo_dp_1k.xcp

TI evm642的源码,给那些没有买TI的评估板,却想要评估板程序的人.

# Xilinx CORE Generator 5.1i
SELECT Asynchronous_FIFO Spartan2 Xilinx,_Inc. 4.0
CSET read_error_sense = active_high
CSET read_count_width = 2
CSET write_acknowledge = false
CSET create_rpm = false
CSET read_acknowledge = false
CSET read_count = false
CSET write_error = false
CSET almost_full_flag = false
CSET almost_empty_flag = false
CSET memory_type = block
CSET read_error = false
CSET fifo_depth = 255
CSET component_name = fifo_dp_1k
CSET input_data_width = 32
CSET write_count = true
CSET write_acknowledge_sense = active_high
CSET read_acknowledge_sense = active_high
CSET write_error_sense = active_high
CSET write_count_width = 8
GENERATE