unpack.vhd

TI evm642的源码,给那些没有买TI的评估板,却想要评估板程序的人.

------------------------------------------------------------------------------
-- *** Disclaimer: This example code is provided with no support. ***
-------------------------------------------------------------------------------
-- File          : unpack.vhd
-- Author        : Shraddha
-- Created       : 
-- Last modified : 01/09/03
-- Project	 : OSD FPGA
-------------------------------------------------------------------------------
-- Description : Unpacks data from FIFO into either 8 bits or 16 bits from 32
-- bits FIFO data
-- 
-------------------------------------------------------------------------------
-- Modification history :
-- 01/09/03 : Shraddha : created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity UNPACK is
port (
    -- from Power Supply
    RESETz              : in std_logic;  -- System Reset
    SRESETz             : in std_logic; 	-- Soft Reset
    
    -- Clock
    VCLK                : in std_logic;  -- 27 Mhz Video Clock
    
    -- from registers
    BUS_WIDTH_8         : in std_logic;  -- Bus width is 8 and not 16

    -- from Control Logic
    DATA_UNPACK         : in std_logic;  -- Unpack signal
    
    -- from Video I/F
    VSYNC 			: in std_logic; -- Vertical sync signal

    -- to/from FIFO
    FIFO_RD             : out std_logic;  -- FIFO read request
    FIFO_DATA           : in std_logic_vector(31 downto 0); -- Data from Y FIFO

    -- To CLUT
    UNPACKED_DATA       : out std_logic_vector(7 downto 0); -- Unpacked data
    CLUT_LOOKUP         : out std_logic
    );
end UNPACK;

architecture RTL of UNPACK is

signal L1_DATA_UNPACK, L2_DATA_UNPACK : std_logic;      -- Pipelined data unpack indicator
signal BYTE_COUNT : std_logic_vector(1 downto 0);  -- Byte count
signal DATA : std_logic_vector(31 downto 0);  -- Pipelined FIFO data
signal CLK_COUNT : std_logic_vector(2 downto 0); -- Clocks counted for FIFO read
signal L1_CLK_COUNT, L2_CLK_COUNT : std_logic_vector(2 downto 0); -- pipelined clock counter

begin	-- RTL

  -- purpose: adds latency to signals
  -- type   : sequential
  LATENCY: process (VCLK, RESETz)
  begin  -- process LATENCY
    if RESETz = '0' or SRESETz = '0' then                -- asynchronous reset (active low)
      L1_DATA_UNPACK <= '0';
      L2_DATA_UNPACK <= '0';
      L1_CLK_COUNT <= "000";
      L2_CLK_COUNT <= "000";
    elsif VCLK'event and VCLK = '1' then  -- rising clock edge
      L1_DATA_UNPACK <= DATA_UNPACK;
      L2_DATA_UNPACK <= L1_DATA_UNPACK;
      L1_CLK_COUNT <= CLK_COUNT;
      L2_CLK_COUNT <= L1_CLK_COUNT;
    end if;
  end process LATENCY;

  -- purpose: Unpacks data from FIFO
  UNPACK: process (VCLK, RESETz)
  begin  -- process UNPACK
    if RESETz = '0' or SRESETz = '0' then                -- asynchronous reset (active low)
      BYTE_COUNT <= (others =>'0');
      UNPACKED_DATA <= (others => '0');
      CLUT_LOOKUP <= '0';
    elsif VCLK'event and VCLK = '1' then  -- rising clock edge
      -- The unpacking is done assuming that the DM642 is operated in little
      -- endian mode.

      -- If video data bus width is 8 bits, unpacking is done every other
      -- clock cycle
      if L2_DATA_UNPACK = '1' then
          if BUS_WIDTH_8 = '1' and L2_CLK_COUNT(0) = '0' then
              case BYTE_COUNT is
                  when "00" =>
                      UNPACKED_DATA(7 downto 0) <= FIFO_DATA(7 downto 0);
                  when "01" =>
                      UNPACKED_DATA(7 downto 0) <= FIFO_DATA(15 downto 8);
                  when "10" =>
                      UNPACKED_DATA(7 downto 0) <= FIFO_DATA(23 downto 16);
                  when "11" =>
                      UNPACKED_DATA(7 downto 0) <= FIFO_DATA(31 downto 24);
                  when others => null;
              end case;
              BYTE_COUNT <= BYTE_COUNT + 1;
          elsif BUS_WIDTH_8 = '0' then
          -- if video data bus width is 16 bits, unpacking is done every clock cycle
              case BYTE_COUNT is
                  when "00" =>
                      UNPACKED_DATA(7 downto 0) <= FIFO_DATA(7 downto 0);
                  when "01" =>
                      UNPACKED_DATA(7 downto 0) <= FIFO_DATA(15 downto 8);
                  when "10" =>
                      UNPACKED_DATA(7 downto 0) <= FIFO_DATA(23 downto 16);
                  when "11" =>
                      UNPACKED_DATA(7 downto 0) <= FIFO_DATA(31 downto 24);
                  when others => null;
               end case;
             BYTE_COUNT <= BYTE_COUNT + 1;
          end if;
          CLUT_LOOKUP <= '1';
      else
      	if VSYNC = '1' then
      		BYTE_COUNT <= "00";
      	else
        		BYTE_COUNT <= BYTE_COUNT;
        end if;
        CLUT_LOOKUP <= '0';
      end if;
    end if;
  end process UNPACK;

  -- purpose: Generates FIFO read signal and reads the FIFO
  FIFO_RD_CTL: process (VCLK, RESETz)
  begin  -- process FIFO_RD_CTL
    if RESETz = '0' or SRESETz = '0' then                -- asynchronous reset (active low)
      FIFO_RD <= '0';
      CLK_COUNT <= "000";
    elsif VCLK'event and VCLK = '1' then  -- rising clock edge
      if DATA_UNPACK = '1' then
          -- if Bus width of Video port is 8 bits data is read out
          -- of the FIFO every eight clock cycles otherwise if the
          -- Video port width is 16 bits, data is read out of the
          -- FIFO every four clock cycles.
          if (BUS_WIDTH_8 = '1' and CLK_COUNT = "000") or
          (BUS_WIDTH_8 = '0' and CLK_COUNT(1 downto 0) = "00") then
              FIFO_RD <= '1';
          else
              FIFO_RD <= '0';
          end if;
      else
        FIFO_RD <= '0';
      end if;
      
      -- The clock count is reset at the beginning of each field to ensure 
      -- new field starts with new word read from the fifo.  The clock count
      -- increments every time DATA_UNPACK is 1.
      if VSYNC = '1' then
      	CLK_COUNT <= "000";
      elsif DATA_UNPACK = '1' then
      	CLK_COUNT <= CLK_COUNT + 1;
      else
      	CLK_COUNT <= CLK_COUNT;
     end if;
    end if;
  end process FIFO_RD_CTL;
  

end RTL;