osd_top.vhd

TI evm642的源码,给那些没有买TI的评估板,却想要评估板程序的人.

    
    -- Clock
    EMIF_CLK            : in std_logic;  -- 100 Mhz EMIF Clock

    -- from EMIF IF
    FIFO_WE             : in std_logic;  -- Write Enable for Y FIFO

    -- from registers
    FIFO_THLD           : in std_logic_vector(11 downto 0);  -- threshold
    EVTS_PER_FIELD      : in std_logic_vector(15 downto 0); 

    -- from Video IF
    VSYNC               : in std_logic; 

    -- From state machine
    EVT_EN              : in std_logic;  -- DMA Events enabled

    -- from FIFO
    FIFO_USED           : in std_logic_vector(7 downto 0);  -- FIFO usage

   -- to DSP
    OSD_EVT             : out std_logic   -- Video Display Event

    );
end component;

component dll_standard 
  port (
    CLKIN               : in  std_logic;
    RESET               : in  std_logic;
    CLK0                : out std_logic;
    CLK90               : out std_logic;
    CLK270              : out std_logic;
    LOCKED              : out std_logic
    );
end component;

component HD_DDR
port (
    -- from Power Supply
    RESETz      : in std_logic;  -- System Reset
    SRESETz     : in std_logic;  -- Soft Reset
    
    -- Clock
    VCLK        : in std_logic;  -- Video Clock
    VCLK_90     : in std_logic;

    -- From registers
    BUS_WIDTH_8 : in std_logic;

    -- from/to OSD mux
    VID_OSD_DATA : in std_logic_vector(19 downto 0);  

    -- To encoder
    PIXCLKI     : out std_logic;
    DENCDATA    : out std_logic_vector(11 downto 0)
    );
end component;

component PLL_SI
port (
    -- from Power Supply
    RESETz              : in std_logic;  -- System Reset
    SRESETz             : in std_logic;  -- Soft reset
    
    -- Clock
    EMIF_CLK            : in std_logic;  -- EMIF Clock
    
    -- From/to Registers
    TX_DATA             : in std_logic_vector(15 downto 0);  -- PLL config data
    TX_START            : in std_logic;  -- Transmit start indicator
    PLL_TX_END          : out std_logic;  -- Transmit End indicator

    -- Output to PLL
    PLL_MC              : out std_logic;  -- PLL Serial clock
    PLL_MD              : out std_logic;  -- PLL Serial Data
    PLL_MS              : out std_logic  -- PLL Select
    );
end component;

component IBUFG
-- synopsys translate_off
   generic(
      TimingChecksOn: Boolean := DefaultTimingChecksOn;
      InstancePath: STRING := "*";
      Xon: Boolean := DefaultXon;
      MsgOn: Boolean := DefaultMsgOn;
      tpd_I_O   : VitalDelayType01 := (0.100 ns, 0.100 ns);
      tipd_I    : VitalDelayType01 := (0.000 ns, 0.000 ns));

-- synopsys translate_on
   port(
      O                 : out STD_ULOGIC;
      I                 : in  STD_ULOGIC);
end component;

signal SRESETz : std_logic;
signal VCLK : std_logic;
signal VCLK_90 : std_logic;
signal VCLK_270 : std_logic;
signal REG_CSlz : std_logic;
signal REG_DSz : std_logic;
signal REG_RWz : std_logic;
signal REG_ADDRb : std_logic_vector(3 downto 0);
signal REG_DATA_INb : std_logic_vector(7 downto 0);
signal REG_DATA_OUTb : std_logic_vector(7 downto 0);
signal FIFO_WE : std_logic;
signal FIFO_DATA_INb : std_logic_vector(31 downto 0);
signal CLUT_WE : std_logic;
signal CLUT_DATA_INb : std_logic_vector(23 downto 0);
signal FIFO_RD : std_logic;
signal FLUSH_FIFO : std_logic;
signal FIFO_DATA : std_logic_vector(31 downto 0);
signal FIFO_FULL : std_logic;
signal FIFO_EMPTY : std_logic;
signal DATA_UNPACK : std_logic;
signal UNPACKED_DATA : std_logic_vector(7 downto 0);
signal OSD_EN : std_logic;
signal CLEAR_CLUT : std_logic;
signal PIXEL_CNT : std_logic_vector(11 downto 0);
signal FIFO_URUN : std_logic;
signal EVT_EN : std_logic;
signal MUX_CTL : std_logic;
signal OSD_DATA : std_logic_vector(15 downto 0);
signal TIED_HIGH : std_logic;
signal FIFO_USED : std_logic_vector(7 downto 0);
signal LOCKED_DLL : std_logic;
signal VID_OSD_DATA : std_logic_vector(19 downto 0);
signal VIDEO_DATA : std_logic_vector(19 downto 0);
signal BUS_WIDTH_8 : std_logic;
signal RESET : std_logic;
signal PLL_TX_DATA : std_logic_vector(15 downto 0);
signal PLL_TX_START : std_logic;
signal SYNC_REG_CSlz : std_logic;
signal SREz : std_logic;
signal SWEz : std_logic;
signal SOEz : std_logic;
signal SADDRb : std_logic_vector(4 downto 0); 
signal SADDRb_22 : std_logic; 
signal SREG_DATA_INb : std_logic_vector(31 downto 0);
signal SREG_DATA_OUTb : std_logic_vector(31 downto 0);
signal PLL_TX_END : std_logic;
signal VSYNC : std_logic;
signal HSYNC : std_logic;
signal AVID : std_logic;
signal CLUT_LOOKUP : std_logic;
signal ALPHA_LSB : std_logic;
signal ALPHA_MSB : std_logic;
signal DLL_RST : std_logic;
signal OSD_XSTART : std_logic_vector(11 downto 0);
signal OSD_YSTART : std_logic_vector(11 downto 0);
signal OSD_XSTOP : std_logic_vector(11 downto 0);
signal OSD_YSTOP : std_logic_vector(11 downto 0);
signal EVTS_PER_FIELD : std_logic_vector(15 downto 0); 
signal CRESETz : std_logic;

begin	-- RTL

  EMIF_IF_MODULE : EMIF_IF
    port map(
      RESETz            => RESETz,
      EMIF_CLK          => EMIF_CLK,
      DM642_AOE_SOEz    => AAOEz,
      DM642_ARE_SREz    => AAREz,
      DM642_AWE_SWEz    => AAWEz,
      DM642_CE1z        => CE1z,
      DM642_CE2z        => CE2z,
      DM642_CE3z        => CE3z,
      DM642_EA_22       => EA_22,
      DM642_EA          => EA(7 downto 3),
      DM642_DATAbt      => ED,
      REG_CSlz          => REG_CSlz,
      REG_DSz           => REG_DSz,
      REG_RWz           => REG_RWz,
      REG_ADDRb         => REG_ADDRb,
      REG_DATA_INb      => REG_DATA_INb,
      REG_DATA_OUTb     => REG_DATA_OUTb,
      SYNC_REG_CSlz     => SYNC_REG_CSlz,
      SREz              => SREz,
      SWEz              => SWEz,
      SOEz              => SOEz,
      SADDRb            => SADDRb,
      SADDRb_22         => SADDRb_22,
      SREG_DATA_INb     => SREG_DATA_INb,
      SREG_DATA_OUTb    => SREG_DATA_OUTb,
      FIFO_WE           => FIFO_WE,
      FIFO_DATA_INb     => FIFO_DATA_INb,
      CLUT_WE           => CLUT_WE,
      CLUT_DATA_INb     => CLUT_DATA_INb,
      DC_EMIF_OEz       => DC_EMIF_OEz,
      DC_EMIF_DIR       => DC_EMIF_DIR
      );
        
  VIDEO_IF_MODULE : VIDEO_IF
    port map(
      RESETz            => RESETz,
      SRESETz           => SRESETz,
      VCLK              => VCLK,
      VCLK_90           => VCLK_90,
      VP2D              => VP2D,
      VP2CTL0           => VP2CTL0,
      VP2CTL1           => VP2CTL1,
      VP2CTL2           => VP2CTL2,
      VIDEO_DATA        => VIDEO_DATA,
      VSYNC             => VSYNC,
      AVID              => AVID,
      HSYNC             => HSYNC,
      DENC_HSYNC        => DENC_HSYNC,
      DENC_VSYNC        => DENC_VSYNC,
      DENC_FIELD        => DENC_FIELD
    );

  REG_MODULE : REG
    port map(
      RESETz            => RESETz,
      EMIF_CLK          => EMIF_CLK,
      REG_DSz           => REG_DSz,
      REG_RWz           => REG_RWz,
      REG_CSlz          => REG_CSlz,
      ADDRb             => REG_ADDRb,
      DATA_INb          => REG_DATA_INb,
      DATA_OUTbt        => REG_DATA_OUTb,
      EINT7             => EINT7,
      OSD_EN            => OSD_EN,
      PIXEL_CNT         => PIXEL_CNT,
      FIFO_URUN         => FIFO_URUN,
      SRESETz 	        => SRESETz,
      BUS_WIDTH_8       => BUS_WIDTH_8,
      CLEAR_CLUT        => CLEAR_CLUT,
      DLL_RST           => DLL_RST,
      DLL_LOCK          => LOCKED_DLL,
      PLL_TX_END        => PLL_TX_END,
      RTS0_A            => RTS0_A,
      RTS0_B            => RTS0_B,
      LED               => LED,
      GPIO              => GPIO,
      FLASH_PAGEz       => FLASH_PAGEz,
      UART_INTA         => UART_INTA,
      UART_INTB         => UART_INTB
    );

  SYNC_REG_MODULE : SYNC_REG
    port map(
      RESETz            => RESETz,
      SRESETz           => SRESETz,
      EMIF_CLK          => EMIF_CLK,
      SYNC_REG_CSlz     => SYNC_REG_CSlz,
      SREz              => SREz,
      SWEz              => SWEz,
      SOEz              => SOEz,
      SADDRb            => SADDRb,
      SADDRb_22         => SADDRb_22,
      SREG_DATA_INb     => SREG_DATA_INb,
      SREG_DATA_OUTb    => SREG_DATA_OUTb,
      OSD_XSTART        => OSD_XSTART,
      OSD_YSTART        => OSD_YSTART,
      OSD_XSTOP         => OSD_XSTOP,
      OSD_YSTOP         => OSD_YSTOP,
      EVTS_PER_FIELD    => EVTS_PER_FIELD,
      PLL_TX_DATA       => PLL_TX_DATA,
      PLL_TX_START      => PLL_TX_START
    );

  FIFO_MODULE : fifo_dp_1k
    port map(
      din               => FIFO_DATA_INb,
      wr_en             => FIFO_WE,
      wr_clk            => EMIF_CLK,
      rd_en             => FIFO_RD,
      rd_clk            => VCLK,
      ainit             => FLUSH_FIFO,
      dout              => FIFO_DATA,
      full              => FIFO_FULL,
      empty             => FIFO_EMPTY,
      wr_count          => FIFO_USED
      );

  UNPACK_MODULE : UNPACK
    port map(
      RESETz            => RESETz,
      SRESETz           => CRESETz,
      VCLK              => VCLK,
      BUS_WIDTH_8       => BUS_WIDTH_8,
      DATA_UNPACK       => DATA_UNPACK,
      VSYNC             => VSYNC,
      FIFO_RD           => FIFO_RD,
      FIFO_DATA         => FIFO_DATA,
      UNPACKED_DATA     => UNPACKED_DATA,
      CLUT_LOOKUP       => CLUT_LOOKUP
      );

  OSD_SM_MODULE : OSD_SM
    port map(
      RESETz            => RESETz,
      SRESETz           => CRESETz,
      VCLK              => VCLK,
      AVID              => AVID,
      VSYNC             => VSYNC,
      HSYNC             => HSYNC,
      OSD_EN            => OSD_EN,
      BUS_WIDTH_8       => BUS_WIDTH_8,
      OSD_XSTART        => OSD_XSTART,
      OSD_YSTART        => OSD_YSTART,
      OSD_XSTOP         => OSD_XSTOP,
      OSD_YSTOP         => OSD_YSTOP,
      FIFO_URUN         => FIFO_URUN,
      FIFO_EMPTY        => FIFO_EMPTY,
      EVT_EN            => EVT_EN,
      FLUSH_FIFO        => FLUSH_FIFO,
      DATA_UNPACK       => DATA_UNPACK,
      MUX_CTL           => MUX_CTL
      );
  
  CLUT_MODULE : OSD_CLUT
    port map (
        RESETz          => RESETz,
        SRESETz         => CRESETz,
        EMIF_CLK        => EMIF_CLK,
        VCLK            => VCLK,
        CLUT_DATA_INb   => CLUT_DATA_INb,
        CLUT_WE         => CLUT_WE,
        BUS_WIDTH_8     => BUS_WIDTH_8,
        CLEAR_CLUT      => CLEAR_CLUT,
        CLUT_DATA_OUTb  => OSD_DATA,
        ALPHA_LSB       => ALPHA_LSB,
        ALPHA_MSB       => ALPHA_MSB,
        CLUT_ADDRb      => UNPACKED_DATA(6 downto 0),
        CLUT_LOOKUP     => CLUT_LOOKUP,
        ALPHA_IN        => UNPACKED_DATA(7)
        );

  OSD_MUX_MODULE : OSD_MUX
    port map(
      RESETz            => RESETz,
      SRESETz           => CRESETz,
      VCLK              => VCLK,
      OSD_DATA          => OSD_DATA,
      ALPHA_LSB         => ALPHA_LSB,
      ALPHA_MSB         => ALPHA_MSB,
      VIDEO_DATA        => VIDEO_DATA,
      MUX_CTL           => MUX_CTL,
      VID_OSD_DATA      => VID_OSD_DATA
      );

  DMA_EVENT_GEN_MODULE : DMA_EVENT_GEN 
    port map(
      RESETz            => RESETz,
      SRESETz           => SRESETz,
      EMIF_CLK          => EMIF_CLK,
      FIFO_WE           => FIFO_WE,
      FIFO_THLD         => PIXEL_CNT,
      EVTS_PER_FIELD    => EVTS_PER_FIELD,
      VSYNC             => VSYNC,
      EVT_EN            => EVT_EN,
      FIFO_USED         => FIFO_USED,
      OSD_EVT           => EINT6
      );

  DLL : dll_standard 
  port map(
    CLKIN               => VP2CLK1,
    RESET               => RESET,
    CLK0                => VCLK,
    CLK90               => VCLK_90,
    CLK270              => VCLK_270,
    LOCKED              => LOCKED_DLL
    );

  DDR_MODULE : HD_DDR
    port map(
      RESETz            => RESETz,
      SRESETz           => CRESETz,
      VCLK              => VCLK,
      VCLK_90           => VCLK_90,
      BUS_WIDTH_8       => BUS_WIDTH_8,
      VID_OSD_DATA      => VID_OSD_DATA,
      PIXCLKI           => PIXCLKI,
      DENCDATA          => DENCDATA
    );
    
  PLL_SI_MODULE : PLL_SI 
     port map(
      RESETz            => RESETz,
      SRESETz           => SRESETz,
      EMIF_CLK          => EMIF_CLK,
      TX_DATA           => PLL_TX_DATA,
      TX_START          => PLL_TX_START,
      PLL_TX_END        => PLL_TX_END,
      PLL_MC            => PLL_MC,
      PLL_MD            => PLL_MD,
      PLL_MS            => PLL_MS
    );



clkpad : IBUFG  port map (I=>PIXCLKO, O=>VP2CLK0);
--  VP2CLK0 <= PIXCLKO;
  TIED_HIGH <= '1';

  -- purpose: resets the DLL
  RESET_DLL: process (EMIF_CLK, RESETz)
  begin  -- process RESET_DLL
    if RESETz = '0' then                -- asynchronous reset (active low)
      RESET <= '1';
    elsif EMIF_CLK'event and EMIF_CLK = '1' then  -- rising clock edge
      if DLL_RST = '1' then
          RESET <= '1';
      else
          RESET <= '0';
      end if;
    end if;
  end process RESET_DLL;
  
  -- purpose: generates reset that combines software reset, hardware reset and DLL lock
  CRESET_CTL : process(VCLK, RESETz)
  begin
      if RESETz = '0' then
          CRESETz <= '0';
      elsif VCLK'event and VCLK = '1' then
          if LOCKED_DLL = '0' or SRESETz = '0' then
              CRESETz <= '0';
          else
              CRESETz <= '1';
          end if;
      end if;
  end process;
    
end RTL;