📄 osd_top.vhd
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------------------------------------------------------------------------------
-- *** Disclaimer: This example code is provided with no support. ***
-------------------------------------------------------------------------------
-- File : osd_top.vhd
-- Author : Shraddha
-- Created :
-- Last modified : June 18th, 2003
-- Project : OSD FPGA
-------------------------------------------------------------------------------
-- Description : Top level module for the OSD FPGA.
--
-------------------------------------------------------------------------------
-- Modification history :
-- Jan 07, 2003 : Shraddha : created
-- April 25, 2003 : Shraddha: Added soft reset to the PLL SI, OSD Mux, and DMA
-- event generation and DDR modules
-- May 02, 2003 : Shraddha : Added DLL_RST to the reset control of DLL module.
-- Routed LOCKED_DLL to register module.
-- May 27, 2003: Shraddha : Added VCLK_90 to video interface module.
-- June 18, 2003: Shraddha : Generated a CRESETz that is a combination of RESETz,
-- SRESETz and LOCKED_DLL and passed that to all modules using VCLK. Removed
-- Monitor_CTL module and signals associated with it (DENC_BLANK, DENC_CSYNC,
-- DENC_VSM, MON_HSYNC, MON_VSYNC). Removed UART_CS signals.
-- Change in OSD requirement to use a OSD window resulted in following
-- changes:
-- 1) Ran VSYNC signal to DMA_EVENT_GENERATOR and UNPACK modules.
-- 2) Ran HSYNC signal to OSD_SM module
-- 3) Added HSYNC signal out to VIDEO_IF
-- 4) Added OSD window parameters to OSD_SM, and SYNC_REG
-- 5) Added EVTS_PER_FIELD parameter to SYNC_REG and DMA_EVENT_GENERATOR modules.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
-- pragma translate_off
use IEEE.VITAL_Timing.all;
library unisim;
use unisim.vcomponents.all;
-- pragma translate_on
entity OSD_TOP is
port (
-- from Power Supply
RESETz : in std_logic; -- System Reset
-- Clock
EMIF_CLK : in std_logic; -- 100 Mhz EMIF Clock
-- from/to DM642 EMIF
CE1z : in std_logic; -- EMIF Memory space 1 enable
CE2z : in std_logic; -- EMIF Memory space 2 enable
CE3z : in std_logic; -- EMIF Memory space 3 enable
AAREz : in std_logic; -- Address strobe/ Read enable
AAWEz : in std_logic; -- Write enable
AAOEz : in std_logic; -- Output enable
ASOE3z : in std_logic; -- Memory space 3 output enable
EA_22 : in std_logic; -- EMIF address bus
EA : in std_logic_vector(7 downto 3);
ED : inout std_logic_vector(31 downto 0); -- EMIF data bus
EINT6 : out std_logic; -- DMA event to DM642
EINT7 : out std_logic; -- Interrupt to DM642
-- from/to DM642 Video Port 2
VP2CLK0 : out std_logic; -- Clock input to DM642 video port
VP2CLK1 : in std_logic; -- Clock output from DM642 video port
VP2CTL0 : in std_logic; -- Video port 2 control 0
VP2CTL1 : in std_logic; -- Video port 2 control 1
VP2CTL2 : in std_logic; -- Video port 2 control 2
VP2D : in std_logic_vector(19 downto 0); -- Video port 2 data bus
-- from/to Video Encoder
DENC_HSYNC : out std_logic;
DENC_VSYNC : out std_logic;
DENC_FIELD : out std_logic;
TVDETECT : in std_logic;
PIXCLKI : out std_logic;
PIXCLKO : in std_logic;
DENCDATA : out std_logic_vector(11 downto 0);
-- from/to Decoders
RTS0_A : in std_logic;
RTS0_B : in std_logic;
-- LED control signals
LED : out std_logic_vector(7 downto 0);
-- GPIOs
GPIO : inout std_logic_vector(7 downto 0);
-- Flash Paging outputs
FLASH_PAGEz : out std_logic_vector(2 downto 0);
-- from/to UART chip
UART_INTA : in std_logic; -- Interrupt from UART A
UART_INTB : in std_logic; -- Interrupt from UART B
UART_RXRDYA : in std_logic; -- RX Ready from UART A
UART_RXRDYB : in std_logic; -- RX Ready from UART B
UART_TXRDYA : in std_logic; -- TX Ready from UART A
UART_TXRDYB : in std_logic; -- TX Ready from UART B
-- TO PLL
PLL_MS : out std_logic; -- PLL select
PLL_MC : out std_logic; -- PLL serial clock
PLL_MD : out std_logic; -- PLL serial data
-- Transceiver controls
DC_EMIF_OEz : out std_logic; -- Output enable
DC_EMIF_DIR : out std_logic -- direction control
);
end OSD_TOP;
architecture RTL of OSD_TOP is
component EMIF_IF
port (
-- from Power Supply
RESETz : in std_logic; -- System Reset
-- Clocky
EMIF_CLK : in std_logic; -- 100 Mhz EMIF Clock
-- from/to C64x
DM642_AOE_SOEz : in std_logic; -- Output Enable
DM642_ARE_SREz : in std_logic; -- Read enable
DM642_AWE_SWEz : in std_logic; -- Write Enable
DM642_CE1z : in std_logic; -- CE1 select
DM642_CE2z : in std_logic; -- CE2 select
DM642_CE3z : in std_logic; -- CE3 select
DM642_EA_22 : in std_logic;
DM642_EA : in std_logic_vector(4 downto 0); -- DM642 address
DM642_DATAbt : inout std_logic_vector(31 downto 0); -- DM642 Data
-- signals from/to Display_reg module
REG_CSlz : out std_logic; -- Chip select for Registers
REG_DSz : out std_logic; -- Data strobe for read/write
REG_RWz : out std_logic; -- Register read/write select
REG_ADDRb : out std_logic_vector(3 downto 0); -- Register address
REG_DATA_INb : out std_logic_vector(7 downto 0); -- Register data
-- in
REG_DATA_OUTb : in std_logic_vector(7 downto 0); -- Register data
-- signals from/to synchronous reg module
SYNC_REG_CSlz : out std_logic; -- Chip select for Sync Registers
SREz : out std_logic; -- Read enable for Sync Registers
SWEz : out std_logic; -- Write enable for Sync Registers
SOEz : out std_logic; -- Output enable for Sync Registers
SADDRb : out std_logic_vector(4 downto 0); -- Address
SADDRb_22 : out std_logic; -- Address bit 22
SREG_DATA_INb : out std_logic_vector(31 downto 0); -- Data in
SREG_DATA_OUTb : in std_logic_vector(31 downto 0); -- Data out
-- out
-- signals to fifo module
FIFO_WE : out std_logic; -- Write Enable for FIFO
FIFO_DATA_INb : out std_logic_vector(31 downto 0); -- FIFO data in
-- signals for CLUT module
CLUT_WE : out std_logic; -- Write enable for CLUT
CLUT_DATA_INb : out std_logic_vector(23 downto 0); -- CLUT data in
-- Transceiver controls
DC_EMIF_OEz : out std_logic;
DC_EMIF_DIR : out std_logic
);
end component;
component VIDEO_IF
port (
-- from Power Supply
RESETz : in std_logic; -- System Reset
SRESETz : in std_logic; -- Soft Reset
-- Clock
VCLK : in std_logic; -- Video Clock
VCLK_90 : in std_logic; -- Video clock phase shifted 90
-- From Video Port
VP2D : in std_logic_vector(19 downto 0); -- Video data
VP2CTL0 : in std_logic; -- Video port control: HSYNC
VP2CTL1 : in std_logic; -- Video port control: VSYNC
VP2CTL2 : in std_logic; -- Video port control: AVID
-- To osd mux
VIDEO_DATA : out std_logic_vector(19 downto 0); -- Video Data
-- To osd sm
VSYNC : out std_logic; -- registered VSYNC
AVID : out std_logic; -- registered AVID
HSYNC : out std_logic; -- registered HSYNC
-- To encoder
DENC_HSYNC : out std_logic; -- HSYNC
DENC_VSYNC : out std_logic; -- VSYNC
DENC_FIELD : out std_logic -- Field
);
end component;
component REG
port (
-- from Power Supply
RESETz : in std_logic; -- System Reset
-- Clock
EMIF_CLK : in std_logic; -- 100 Mhz EMIF Clock
-- from/to C6A
REG_DSz : in std_logic; -- Data Strobe
REG_RWz : in std_logic; -- Read/Write Signal
REG_CSlz : in std_logic; -- Registers chip select
ADDRb : in std_logic_vector(3 downto 0); -- Address
DATA_INb : in std_logic_vector(7 downto 0); -- Data in
DATA_OUTbt : out std_logic_vector(7 downto 0); -- Data out
EINT7 : out std_logic; -- Interrupt to DM642
-- Control / Status
OSD_EN : out std_logic; -- OSD enabled
PIXEL_CNT : out std_logic_vector(11 downto 0); -- DMA threshold
FIFO_URUN : in std_logic; -- FIFO underrun indicator
SRESETz : out std_logic; -- Soft reset
BUS_WIDTH_8 : out std_logic; -- Bus width indicator
CLEAR_CLUT : out std_logic; -- Clear CLUT indicator
DLL_RST : out std_logic; -- DLL reset signal
DLL_LOCK : in std_logic; -- DLL LOCK signal status
-- From PLL Serial Inteface
PLL_TX_END : in std_logic; -- PLL transmission complete flag
-- From/to Decoders
RTS0_A : in std_logic; -- interrupt source from decoder
RTS0_B : in std_logic; -- interrupt source from decoder
-- LED control signals
LED : out std_logic_vector(7 downto 0); -- LED control
-- GPIOs
GPIO : inout std_logic_vector(7 downto 0); -- GPIOs
-- Flash signals
FLASH_PAGEz : out std_logic_vector(2 downto 0); -- Paging for Flash
-- UART signals
UART_INTA : in std_logic; -- Interrupt from UART A
UART_INTB : in std_logic -- Interrupt from UART B
);
end component;
component SYNC_REG
port (
-- from Power Supply
RESETz : in std_logic; -- System Reset
SRESETz : in std_logic; -- Soft Reset
-- Clock
EMIF_CLK : in std_logic; -- 100 Mhz EMIF Clock
-- from/to EMIF IF
SYNC_REG_CSlz : in std_logic; -- Sync chip select
SREz : in std_logic; -- Read enable
SWEz : in std_logic; -- Write enable
SOEz : in std_logic; -- Output enable
SADDRb : in std_logic_vector(4 downto 0); -- Address
SADDRb_22 : in std_logic; -- Address bit 22
SREG_DATA_INb : in std_logic_vector(31 downto 0); -- Data in
SREG_DATA_OUTb : out std_logic_vector(31 downto 0); -- Data out
-- To OSD_SM
OSD_XSTART : out std_logic_vector(11 downto 0); -- OSD xstart pixel
OSD_YSTART : out std_logic_vector(11 downto 0); -- OSD ystart line
OSD_XSTOP : out std_logic_vector(11 downto 0); -- OSD xstop pixel
OSD_YSTOP : out std_logic_vector(11 downto 0); -- OSD ystop line
EVTS_PER_FIELD : out std_logic_vector(15 downto 0);
-- To PLL_SI
PLL_TX_DATA : out std_logic_vector(15 downto 0);
PLL_TX_START : out std_logic
);
end component;
component fifo_dp_1k
port (
din : IN std_logic_VECTOR(31 downto 0);
wr_en : IN std_logic;
wr_clk : IN std_logic;
rd_en : IN std_logic;
rd_clk : IN std_logic;
ainit : IN std_logic;
dout : OUT std_logic_VECTOR(31 downto 0);
full : OUT std_logic;
empty : OUT std_logic;
wr_count : OUT std_logic_VECTOR(7 downto 0));
end component;
-- XST black box declaration
attribute box_type : string;
attribute box_type of fifo_dp_1k: component is "black_box";
component UNPACK
port (
-- from Power Supply
RESETz : in std_logic; -- System Reset
SRESETz : in std_logic;
-- Clock
VCLK : in std_logic; -- 27 Mhz Video Clock
-- from registers
BUS_WIDTH_8 : in std_logic; -- Bus width is 8 and not 16
-- from Control Logic
DATA_UNPACK : in std_logic; -- Unpack signal
-- from Video I/F
VSYNC : in std_logic; -- Vertical sync signal
-- to/from FIFO
FIFO_RD : out std_logic; -- FIFO read request
FIFO_DATA : in std_logic_vector(31 downto 0); -- Data from Y FIFO
-- To CLUT
UNPACKED_DATA : out std_logic_vector(7 downto 0); -- Unpacked data
CLUT_LOOKUP : out std_logic
);
end component;
component OSD_SM
port (
-- from Power Supply
RESETz : in std_logic; -- System Reset
SRESETz : in std_logic; -- Soft Reset
-- Clock
VCLK : in std_logic; -- Video Clock
-- Video Port controls
AVID : in std_logic; -- Active Video
VSYNC : in std_logic; -- Vertical Sync
HSYNC : in std_logic; -- Horizontal Sync
-- from/to Display registers
OSD_EN : in std_logic; -- Enable OSD
BUS_WIDTH_8 : in std_logic;
OSD_XSTART : in std_logic_vector(11 downto 0); -- OSD xstart pixel
OSD_YSTART : in std_logic_vector(11 downto 0); -- OSD ystart pixel
OSD_XSTOP : in std_logic_vector(11 downto 0); -- OSD xtop pixel
OSD_YSTOP : in std_logic_vector(11 downto 0); -- OSD ystop pixel
FIFO_URUN : out std_logic; -- FIFO underrun indicator
-- from FIFO
FIFO_EMPTY : in std_logic; -- FIFOs are empty
-- To dma event generator
EVT_EN : out std_logic; -- Enable DMA events
-- To FIFOs
FLUSH_FIFO : out std_logic; -- Flush FIFOs
-- To Unpack module
DATA_UNPACK : out std_logic; -- Unpack data indicator
-- mux
MUX_CTL : out std_logic -- BT656 mux control
);
end component;
component OSD_CLUT
port (
-- from Power Supply
RESETz : in std_logic; -- System Reset
SRESETz : in std_logic;
-- Clock
EMIF_CLK : in std_logic;
VCLK : in std_logic; -- 27 Mhz Video Clock
-- From EMIF_IF
CLUT_DATA_INb : in std_logic_vector(23 downto 0); -- CLUT data
CLUT_WE : in std_logic; -- CLUT write enable
-- From registers
BUS_WIDTH_8 : in std_logic; -- Bus width is 8 and not 16
CLEAR_CLUT : in std_logic; -- Clear the CLUT write counters
-- To OSD_MUX
CLUT_DATA_OUTb : out std_logic_vector(15 downto 0); -- CLUT/OSD Data
ALPHA_LSB : out std_logic;
ALPHA_MSB : out std_logic;
-- from Unpack
CLUT_ADDRb : in std_logic_vector(6 downto 0); -- CLUT Address
CLUT_LOOKUP : in std_logic;
ALPHA_IN : in std_logic
);
end component;
component OSD_MUX
port (
-- from Power Supply
RESETz : in std_logic; -- System Reset
SRESETz : in std_logic; -- Soft Reset
-- Clock
VCLK : in std_logic; -- 27 Mhz Video Clock
-- From CLUT
OSD_DATA : in std_logic_vector(15 downto 0); -- OSD data
-- From Unpack
ALPHA_LSB : in std_logic; -- Alpha for LSB data
ALPHA_MSB : in std_logic; -- Alpha for MSB data
-- From Video I/F
VIDEO_DATA : in std_logic_vector(19 downto 0); -- Video Data
-- From State machine
MUX_CTL : in std_logic; -- Control for the multiplexer
-- To Video Output Module
VID_OSD_DATA : out std_logic_vector(19 downto 0) -- Multiplexed data
);
end component;
component DMA_EVENT_GEN
port (
-- from Power Supply
RESETz : in std_logic; -- System Reset
SRESETz : in std_logic; -- Soft Reset
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