ddrfd.vhd

TI evm642的源码,给那些没有买TI的评估板,却想要评估板程序的人.

------------------------------------------------------------------------------
-- *** Disclaimer: This example code is provided with no support. ***
------------------------------------------------------------------------------
-- File          : ddrfd.vhd
-- Author        : Shraddha
-- Created       : 
-- Last modified : Jan 31, 2003
-- Project	 : OSD FPGA
------------------------------------------------------------------------------
-- Description : Shifts out data on rising and falling clock edges of the
-- clock.  This implements the DDR functionality.
-- 
------------------------------------------------------------------------------
-- Modification history :
-- Jan 31, 2003 : Shraddha : created
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
-- pragma translate_on

entity DDRFD is
    port (
        DR      : in  std_logic;
        DF      : in std_logic;
        C       : in std_logic;
        RST     : in std_logic;
        Q       : out std_logic
        );
end DDRFD;

architecture RTL of DDRFD is

component LDC
   port(
      D         : in STD_ULOGIC;
      G         : in STD_ULOGIC;
      CLR       : in STD_ULOGIC;
      Q         : out STD_ULOGIC
      );
end component;

component LDC_1
   port(
      D         : in STD_ULOGIC;
      G         : in STD_ULOGIC;
      CLR       : in STD_ULOGIC;
      Q         : out STD_ULOGIC
      );
end component;

component INV
   port(
      I         : in STD_ULOGIC;
      O         : out STD_ULOGIC
      );
end component;

component DDROUT
   port(
      DR        : in STD_ULOGIC;
      DF        : in STD_ULOGIC;
--	  RST 		: in STD_ULOGIC;
      C         : in STD_ULOGIC;
      LRR       : in STD_ULOGIC;
      LRF       : in STD_ULOGIC;
      Q         : out STD_ULOGIC
      );
end component;


signal LRF, LRR, nLRF: std_logic;

begin

    LRF_MODULE : LDC_1
        port map (
            D   => LRR,
            G   => C,
            CLR => RST,
            Q   => LRF
            );

    INVLRF : INV
        port map (
            I   => LRF,
            O   => nLRF
            );

    LRR_MODULE : LDC
        port map (
            D   => nLRF,
            G   => C,
            CLR => RST,
            Q   => LRR
            );

    DDROUT_MODULE : DDROUT
        port map (
            DR  => DR,
            DF  => DF,
--			RST => RST,
              C   => C,
            LRR => LRR,
            LRF => LRF,
            Q   => Q
            );

    
end RTL;