dll_standard.vhd

TI evm642的源码,给那些没有买TI的评估板,却想要评估板程序的人.

------------------------------------------------------------------------------
-- *** Disclaimer: This example code is provided with no support. ***
------------------------------------------------------------------------------
-- File          : dll_standard.vhd
-- Author        : Shraddha
-- Created       : 
-- Last modified : 05/02/03
-- Project	 : OSD FPGA
------------------------------------------------------------------------------
-- Description : This implements the DLL for video clock.  It outputs clocks
-- that are in phase with DLL input clock, 90 degrees out of phase with DLL
-- input clock and 270 degrees out of phase with DLL input clock.
-- 
------------------------------------------------------------------------------
-- Modification history :
-- Jan 9th, 2003 : Shraddha : created
-- 05/02/03: Shraddha : Removed OBUF from the LOCKED signal.  This will allow
-- us to route this signal to a register.
------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
use IEEE.VITAL_Timing.all;
library unisim;
use unisim.vcomponents.all;
-- pragma translate_on

entity dll_standard is
    port (CLKIN : in  std_logic;
          RESET : in  std_logic;
          CLK0  : out std_logic;
          CLK90 : out std_logic;
          CLK270 : out std_logic;
          LOCKED: out std_logic);
end dll_standard;

architecture structural of dll_standard is

component IBUFG
-- synopsys translate_off
   generic(
      TimingChecksOn: Boolean := DefaultTimingChecksOn;
      InstancePath: STRING := "*";
      Xon: Boolean := DefaultXon;
      MsgOn: Boolean := DefaultMsgOn;
      tpd_I_O                        :	VitalDelayType01 := (0.100 ns, 0.100 ns);
      tipd_I                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

-- synopsys translate_on
   port(
      O                              :	out   STD_ULOGIC;
      I                              :	in    STD_ULOGIC);
end component;


component CLKDLL
-- synopsys translate_off
    generic ( TimingChecksOn : Boolean := DefaultTimingChecksOn;
              InstancePath : STRING := "*";
              Xon  : Boolean := DefaultXon;
             MsgOn : Boolean := DefaultMsgOn;

             tipd_CLKIN   : VitalDelayType01 := (0.000 ns, 0.000 ns);
             tipd_CLKFB   : VitalDelayType01 := (0.000 ns, 0.000 ns);
             tipd_RST     : VitalDelayType01 := (0.000 ns, 0.000 ns);

             tpd_CLKIN_LOCKED  : VitalDelayType01 := (0.100 ns, 0.100 ns);

             tperiod_CLKIN_POSEDGE     : VitalDelayType  := 0.010 ns;
             MAXPERCLKIN       : time := 100 ns;

             tpw_CLKIN_posedge : VitalDelayType  := 0.010 ns;
             tpw_CLKIN_negedge : VitalDelayType  := 0.010 ns;

             tpw_RST_posedge   : VitalDelayType  := 0.010 ns;

              DUTY_CYCLE_CORRECTION : Boolean := TRUE;
              CLKDV_DIVIDE : real := 2.0);

-- synopsys translate_on
    port ( CLKIN   : in  std_ulogic := '0';
           CLKFB   : in  std_ulogic := '0';
           RST     : in  std_ulogic := '0';
           CLK0    : out std_ulogic := '0';
           CLK90   : out std_ulogic := '0';
           CLK180  : out std_ulogic := '0';
           CLK270  : out std_ulogic := '0';
           CLK2X   : out std_ulogic := '0';
           CLKDV   : out std_ulogic := '0';
           LOCKED  : out std_ulogic := '0');
end component;
component BUFG
-- synopsys translate_off
   generic(
      TimingChecksOn: Boolean := DefaultTimingChecksOn;
      InstancePath: STRING := "*";
      Xon: Boolean := DefaultXon;
      MsgOn: Boolean := DefaultMsgOn;
      tpd_I_O                        :	VitalDelayType01 := (0.100 ns, 0.100 ns);
      tipd_I                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

-- synopsys translate_on
   port(
      O                              :	out   STD_ULOGIC;
      I                              :	in    STD_ULOGIC);
end component;
component OBUF
-- synopsys translate_off
   generic(
      TimingChecksOn: Boolean := DefaultTimingChecksOn;
      InstancePath: STRING := "*";
      Xon: Boolean := DefaultXon;
      MsgOn: Boolean := DefaultMsgOn;
      tpd_I_O                        :	VitalDelayType01 := (0.100 ns, 0.100 ns);
      tipd_I                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

-- synopsys translate_on
   port(
      O                              :	out   STD_ULOGIC;
      I                              :	in    STD_ULOGIC);
end component;


signal CLKIN_w, RESET_w, CLK0_dll, CLK90_dll, CLK0_g, CLK90_g, CLK270_dll, LOCKED_dll : std_logic;

begin 

clkpad : IBUFG  port map (I=>CLKIN, O=>CLKIN_w);

dll    : CLKDLL port map (CLKIN=>CLKIN_w, CLKFB=>CLK0_g, RST=>RESET,
                          CLK0=>CLK0_dll, CLK90=>CLK90_dll, CLK180=>open,
                          CLK270=>CLK270_dll, CLK2X=>open,  CLKDV=>open,
                          LOCKED=>LOCKED_dll);

clkg   : BUFG   port map (I=>CLK0_dll,   O=>CLK0_g);

CLK0 <= CLK0_g;
CLK90 <= CLK90_dll;
LOCKED <= LOCKED_dll;
CLK270 <= CLK270_dll;

end structural;