video_if.vhd

TI evm642的源码,给那些没有买TI的评估板,却想要评估板程序的人.

------------------------------------------------------------------------------
-- *** Disclaimer: This example code is provided with no support. ***
------------------------------------------------------------------------------
-- File          : video_if.vhd
-- Author        : Shraddha
-- Created       : 
-- Last modified : Feb 14, 2003
-- Project	 : OSD FPGA
------------------------------------------------------------------------------
-- Description : Interfaces to Video Port
-- 
------------------------------------------------------------------------------
-- Modification history :
-- Feb 14, 2003 : Shraddha : created
-- May 01, 2003 : Shraddha : Added one more latency in the DENC_HSYNC and
-- DENC_VSYNC paths
-- May 27, 2003 : Shraddha : Moved DENC_HSYNC and DENC_VSYNC from VCLK domain
-- to VCLK_90 domain.  Brought in VCLK_90 clock to video interface module.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity VIDEO_IF is
port (
    -- from Power Supply
    RESETz              : in std_logic;  -- System Reset
    SRESETz 			: in std_logic; 	-- Soft Reset
    
    -- Clock
    VCLK                : in std_logic;  
    VCLK_90 			: in std_logic;
    
    -- From Video Port
    VP2D                : in std_logic_vector(19 downto 0);  -- Video data
    VP2CTL0             : in std_logic;
    VP2CTL1             : in std_logic;
    VP2CTL2             : in std_logic;

    -- To osd mux
    VIDEO_DATA          : out std_logic_vector(19 downto 0);  -- Video Data

    -- To osd sm
    VSYNC               : out std_logic;
    AVID                : out std_logic;
		HSYNC								: out std_logic;

    -- To encoder
    DENC_HSYNC          : out std_logic;
    DENC_VSYNC          : out std_logic;
    DENC_FIELD          : out std_logic
    );
end VIDEO_IF;

architecture RTL of VIDEO_IF is

signal L1_VP2D, L2_VP2D, L3_VP2D, L4_VP2D, L5_VP2D, L6_VP2D, L7_VP2D : std_logic_vector(19 downto 0);
signal L1_VP2CTL0, L2_VP2CTL0, L3_VP2CTL0, L4_VP2CTL0, L5_VP2CTL0,
    L6_VP2CTL0, L7_VP2CTL0,
    L8_VP2CTL0, L9_VP2CTL0, L10_VP2CTL0 : std_logic;
signal L1_VP2CTL1, L2_VP2CTL1, L3_VP2CTL1, L4_VP2CTL1, L5_VP2CTL1, L6_VP2CTL1, L7_VP2CTL1,
    L8_VP2CTL1, L9_VP2CTL1, L10_VP2CTL1  : std_logic;
signal L1S_VP2CTL0 : std_logic;
signal L1S_VP2CTL1 : std_logic;
  
begin	-- RTL


  -- purpose: adds latency
  LATENCY: process (VCLK, RESETz)
  begin  -- process LATENCY
    if RESETz = '0' or SRESETz = '0' then                -- asynchronous reset (active low)
      L1_VP2D <= ( others => '0');
      L2_VP2D <= ( others => '0');
      L3_VP2D <= ( others => '0');
      L4_VP2D <= ( others => '0');
      L5_VP2D <= ( others => '0');
      L6_VP2D <= ( others => '0');
      L7_VP2D <= ( others => '0');
      VIDEO_DATA <= ( others => '0');
      L1_VP2CTL0 <= '0';
      L1_VP2CTL1 <= '0';
      VSYNC <= '0';
      AVID <= '0';
			HSYNC <= '0';
    elsif VCLK'event and VCLK = '1' then  -- rising clock edge
      L1_VP2D <= VP2D;
      L2_VP2D <= L1_VP2D;
      L3_VP2D <= L2_VP2D;
      L4_VP2D <= L3_VP2D;
      L5_VP2D <= L4_VP2D;
      L6_VP2D <= L5_VP2D;
      L7_VP2D <= L6_VP2D;
      VIDEO_DATA <= L7_VP2D;

      L1_VP2CTL0 <= VP2CTL0;

      L1_VP2CTL1 <= VP2CTL1;

      VSYNC <= VP2CTL1;
      AVID <= VP2CTL2;
      HSYNC <= VP2CTL0;
    end if;
  end process LATENCY;

  -- purpose: synchronizes to VCLK_90 and adds latency
  SYNC_LATENCY: process (VCLK_90, RESETz)
  begin  -- process SYNC_LATENCY
    if RESETz = '0' or SRESETz = '0' then                -- asynchronous reset (active low)
	  L1S_VP2CTL0 <= '0';
      L2_VP2CTL0 <= '0';
      L3_VP2CTL0 <= '0';
      L4_VP2CTL0 <= '0';
      L5_VP2CTL0 <= '0';
      L6_VP2CTL0 <= '0';
      L7_VP2CTL0 <= '0';
      L8_VP2CTL0 <= '0';
      L9_VP2CTL0 <= '0';
      L10_VP2CTL0 <= '0';
       DENC_HSYNC <= '0';
	  L1S_VP2CTL1 <= '0';
      L2_VP2CTL1 <= '0';
      L3_VP2CTL1 <= '0';
      L4_VP2CTL1 <= '0';
      L5_VP2CTL1 <= '0';
      L6_VP2CTL1 <= '0';
      L7_VP2CTL1 <= '0';
      L8_VP2CTL1 <= '0';
      L9_VP2CTL1 <= '0';
      L10_VP2CTL1 <= '0';
      DENC_VSYNC <= '0';
    elsif VCLK_90'event and VCLK_90 = '1' then  -- rising clock edge
	  L1S_VP2CTL0 <= L1_VP2CTL0;
      L2_VP2CTL0 <= L1S_VP2CTL0;
      L3_VP2CTL0 <= L2_VP2CTL0;
      L4_VP2CTL0 <= L3_VP2CTL0;
      L5_VP2CTL0 <= L4_VP2CTL0;
      L6_VP2CTL0 <= L5_VP2CTL0;
      L7_VP2CTL0 <= L6_VP2CTL0;
      L8_VP2CTL0 <= L7_VP2CTL0;
      L9_VP2CTL0 <= L8_VP2CTL0;
      L10_VP2CTL0 <= L9_VP2CTL0;
      DENC_HSYNC <= L10_VP2CTL0;
      
      L1S_VP2CTL1 <= L1_VP2CTL1;
      L2_VP2CTL1 <= L1S_VP2CTL1;
      L3_VP2CTL1 <= L2_VP2CTL1;
      L4_VP2CTL1 <= L3_VP2CTL1;
      L5_VP2CTL1 <= L4_VP2CTL1;
      L6_VP2CTL1 <= L5_VP2CTL1;
      L7_VP2CTL1 <= L6_VP2CTL1;
      L8_VP2CTL1 <= L7_VP2CTL1;
      L9_VP2CTL1 <= L8_VP2CTL1;
      L10_VP2CTL1 <= L9_VP2CTL1;
       DENC_VSYNC <= L10_VP2CTL1;

    end if;
  end process SYNC_LATENCY;


  DENC_FIELD <= '0';
end RTL;