reg.vhd

TI evm642的源码,给那些没有买TI的评估板,却想要评估板程序的人.

    -- purpose: This process reads from asynchronous registers
    REG_READ: process(EMIF_CLK, RESETz)   
    begin
    
        if RESETz = '0' then
            DATA_OUTbt <= (others => '0');
        elsif EMIF_CLK'event and EMIF_CLK = '1' then
            DATA_OUTbt <= (others => '0');
            case ADDRb(3 downto 0) is
                when "0000" =>
                    DATA_OUTbt(1) <= P_OSD_EN;
                    DATA_OUTbt(2) <= P_INTEN;
                    DATA_OUTbt(3) <= P_BUS_WIDTH_8;
                    DATA_OUTbt(4) <= P_CLEAR_CLUT;
                    DATA_OUTbt(5) <= P_DLL_RST;
                when "0001" =>
                    DATA_OUTbt(7 downto 0) <= P_PIXEL_CNT(7 downto 0);
                when "0010" =>
                    DATA_OUTbt(3 downto 0) <= P_PIXEL_CNT(11 downto 8);
                when "0011" =>
                    DATA_OUTbt(6 downto 0) <= S_DLL_LOCK & PLL_TX_END_FLAG &
                                              S_UART_INTB & S_UART_INTA &
                                              S_RTS0_B & S_RTS0_A &
                                              S_FIFO_URUN;
                when "0100" =>
                    DATA_OUTbt(4 downto 0) <= P_INT_MASK;
                when "0101" =>
                    DATA_OUTbt(7 downto 0) <= GPIO_DIR;
                when "0110" =>
                    DATA_OUTbt(7 downto 0) <= GPIO_READ;
                when "0111" =>
                    DATA_OUTbt(7 downto 0) <= P_LED;
                when "1000" =>
                    DATA_OUTbt(2 downto 0) <= P_FLASH_PAGEz;
                when "1111" =>
                    DATA_OUTbt(7 downto 0) <= "00000100";  -- RTL version
                when others =>
                    DATA_OUTbt <= (others => '0');
            end case;
        end if;
    end process REG_READ;

    -- purpose: generates and clears interrupt to the DM642
    INT_GEN: process (EMIF_CLK, RESETz)
    begin  -- process INT_GEN
        if RESETz = '0' or P_SRESETz = '0' then -- asynchronous reset (active low)
            EINT7 <= '0';
            L1_FIFO_URUN <= '0';
        elsif EMIF_CLK'event and EMIF_CLK = '1' then  -- rising clock edge
            -- The FIFO underrun is the only interrupt source that is
            -- generated inside the FPGA.  The FIFO_URUN signal once asserted,
            -- remains asserted till the FIFO is no longer empty.  Hence, the
            -- interrupt logic looks at the transition from low to high of
            -- this signal to generate an interrupt to the DSP instead of
            -- looking at the level of this signal.  Otherwise, potentially
            -- the interrupt could be asserted multiple times for this
            -- interrupt source.

            -- For the other interrupt sources, the FPGA cannot tell whether
            -- there is a valid reason for the interrupt source signal to
            -- remain asserted.  Hence, it assumes that if the signal is
            -- asserted it means an interrupt is pending.  The responsibility
            -- is left to software to ensure that before getting out of the
            -- interrupt service routine it clears the interrupt from the
            -- interrupt source.  The ISR can clear the INTEN bit in the OSD
            -- Control Register at the beginning of the ISR, clear the
            -- interrupts pending, and the set the INTEN bit again to ensure
            -- that same interrupt does not cause multiple interrupts to the DSP.
            if ((S_FIFO_URUN = '1' and L1_FIFO_URUN = '0' and URUN_INTEN = '1') or
                (S_UART_INTA = '1' and UARTA_INTEN = '1') or
                (S_UART_INTB = '1' and UARTB_INTEN = '1') or
                (S_RTS0_A = '1' and RTS0A_INTEN = '1') or
                (S_RTS0_B = '1' and RTS0B_INTEN = '1'))and
                P_INTEN = '1' then
                EINT7 <= '1';
            elsif REG_CSlz = '0' and REG_RWz = '1' and ADDRb = "0011" then
                EINT7 <= '0';
            end if;
            L1_FIFO_URUN <= S_FIFO_URUN;
        end if;
    end process INT_GEN;

    -- purpose: synchronizes status signals to EMIF clock
    SYNC_SIGNALS: process (EMIF_CLK, RESETz)
    begin  -- process SYNC_SIGNALS
        if RESETz = '0' or P_SRESETz = '0' then -- asynchronous reset (active low)
            S_FIFO_URUN <= '0';
            S_UART_INTA <= '0';
            S_UART_INTB <= '0';
            S_RTS0_A <= '0';
            S_RTS0_B <= '0';
            S_DLL_LOCK <= '0';
        elsif EMIF_CLK'event and EMIF_CLK = '1' then  -- rising clock edge
            S_FIFO_URUN <= FIFO_URUN;
            S_UART_INTA <= UART_INTA;
            S_UART_INTB <= UART_INTB;
            S_RTS0_A <= RTS0_A;
            S_RTS0_B <= RTS0_B;
            S_DLL_LOCK <= DLL_LOCK;
        end if;
    end process SYNC_SIGNALS;

    -- purpose: controls PLL transmit end flag
    PLL_FLAG : process (EMIF_CLK, RESETz)
      
    begin  -- process PLL_FLAG
        if RESETz = '0' or P_SRESETz = '0' then
            PLL_TX_END_FLAG <= '0';
            L1_PLL_TX_END <= '0';
            L1_REG_DSz <= '1';
        elsif EMIF_CLK'event and EMIF_CLK = '1' then
            -- This flag is set whenever the PLL_TX_END signal from the PLL_SI
            -- module is asserted.  Reading the OSD Status Register resets
            -- this flag.
            if PLL_TX_END = '1' and L1_PLL_TX_END = '0' then
                PLL_TX_END_FLAG <= '1';
            elsif PLL_FLAG_RST = '1' then
                PLL_TX_END_FLAG <= '0';
            end if;

            -- This logic detects a read to the OSD status register.  The flag
            -- reset bit i set after the rising edge of data strobe to ensure
            -- the DSP reads the flag correctly.
            if ADDRb(3 downto 0) = "0011"  and REG_CSlz = '0' and
            REG_RWz = '0' and REG_DSz = '1' and L1_REG_DSz = '0' and DATA_INb(5) = '1' then
                PLL_FLAG_RST <= '1';
            else
                PLL_FLAG_RST <= '0';                
            end if;

            L1_PLL_TX_END <= PLL_TX_END;
            L1_REG_DSz <= REG_DSz;
        end if;
    end process PLL_FLAG;



    -- GPIO Out Control
    GPIO(0) <= GPIO_REG(0) when GPIO_DIR(0) = '1' else
               'Z';
    GPIO(1) <= GPIO_REG(1) when GPIO_DIR(1) = '1' else
               'Z';
    GPIO(2) <= GPIO_REG(2) when GPIO_DIR(2) = '1' else
               'Z';
    GPIO(3) <= GPIO_REG(3) when GPIO_DIR(3) = '1' else
               'Z';
    GPIO(4) <= GPIO_REG(4) when GPIO_DIR(4) = '1' else
               'Z';
    GPIO(5) <= GPIO_REG(5) when GPIO_DIR(5) = '1' else
               'Z';
    GPIO(6) <= GPIO_REG(6) when GPIO_DIR(6) = '1' else
               'Z';
    GPIO(7) <= GPIO_REG(7) when GPIO_DIR(7) = '1' else
               'Z';
  
    -- GPIO Read
    GPIO_READ(0) <= GPIO(0) when GPIO_DIR(0) = '0' else
                    GPIO_REG(0);
    GPIO_READ(1) <= GPIO(1) when GPIO_DIR(1) = '0' else
                    GPIO_REG(1) ;
    GPIO_READ(2) <= GPIO(2) when GPIO_DIR(2) = '0' else
                    GPIO_REG(2);
    GPIO_READ(3) <= GPIO(3) when GPIO_DIR(3) = '0' else
                    GPIO_REG(3);
    GPIO_READ(4) <= GPIO(4) when GPIO_DIR(4) = '0' else
                    GPIO_REG(4);
    GPIO_READ(5) <= GPIO(5) when GPIO_DIR(5) = '0' else
                    GPIO_REG(5);
    GPIO_READ(6) <= GPIO(6) when GPIO_DIR(6) = '0' else
                    GPIO_REG(6);
    GPIO_READ(7) <= GPIO(7) when GPIO_DIR(7) = '0' else
                    GPIO_REG(7);

    UARTB_INTEN <= P_INT_MASK(4);
    UARTA_INTEN <= P_INT_MASK(3);
    RTS0B_INTEN <= P_INT_MASK(2);
    RTS0A_INTEN <= P_INT_MASK(1);
    URUN_INTEN <= P_INT_MASK(0);
    FLASH_PAGEz <= P_FLASH_PAGEz;
    LED <= P_LED;
    OSD_EN <= P_OSD_EN;
    SRESETz <= P_SRESETz;
    BUS_WIDTH_8 <= P_BUS_WIDTH_8;
    PIXEL_CNT <= P_PIXEL_CNT;
    CLEAR_CLUT <= P_CLEAR_CLUT;
    DLL_RST <= P_DLL_RST;
 
end RTL;