reg.vhd

TI evm642的源码,给那些没有买TI的评估板,却想要评估板程序的人.

------------------------------------------------------------------------------
-- *** Disclaimer: This example code is provided with no support. ***
------------------------------------------------------------------------------
-- File          : reg.vhd
-- Author        : Shraddha
-- Created       : 
-- Last modified : June 02, 2003
-- Project	 : OSD FPGA
------------------------------------------------------------------------------
-- Description :
-- This is the Asynchronous Registers module of the OSD FPGA.
------------------------------------------------------------------------------
-- Modification history :
-- Jan 07, 2003 : Shraddha : created
-- April 25, 2003 : Shraddha : Changed the clearing of the PLL_TX_END_FLAG.
-- The flag was getting cleared before the end of strobe period of EMIF
-- asynchronous memory cycle.  This caused the DSP to read incorrect values
-- for the flag.  The design is changed to reset the flag only after the
-- strobe period is over.
-- Also added version register to the register space.  The version is set
-- to 01h for this RTL.
-- May 01, 2003 : Changed version to 02h.
-- May 02, 2003 : Shraddha : Added a bit in OSD Control Register to reset the
-- Video DLL.  Also added a bit to the Interrupt Status register to show the
-- status of the LOCK bit of Video DLL.  Changed version to 03h.
-- June 02, 2003 : Shraddha : Changed the PLL_TX_END_FLAG reset logic.  Now
-- the flag gets reset when a '1' is written to the Interrupt Status
-- Registers 5th bit.
-- Changed the version to 04h.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity REG is
port (
    -- from Power Supply
    RESETz      : in std_logic;  -- System Reset
    
    -- Clock
    EMIF_CLK    : in std_logic;  -- 100 Mhz EMIF Clock

    -- from/to EMIF_IF module
    REG_DSz     : in std_logic;  -- Data Strobe
    REG_RWz     : in std_logic;  -- Read/Write Signal
    REG_CSlz     : in std_logic; -- Registers chip select
    ADDRb       : in std_logic_vector(3 downto 0);  -- Address     
    DATA_INb    : in std_logic_vector(7 downto 0);  -- Data in 
    DATA_OUTbt  : out std_logic_vector(7 downto 0); -- Data out
    EINT7       : out std_logic; -- Interrupt to DM642

    -- Control / Status
    OSD_EN      : out std_logic; -- OSD Enable indicator
    PIXEL_CNT   : out std_logic_vector(11 downto 0);  -- FIFO threshold for
                                                      -- DMA event
    FIFO_URUN   : in std_logic;  -- FIFO underrun indicator
    SRESETz     : out std_logic; -- Soft Reset indicator
    BUS_WIDTH_8 : out std_logic; -- Video Port Bus width indicator
    CLEAR_CLUT  : out std_logic; -- Clear CLUT indicator
    DLL_RST     : out std_logic;
    DLL_LOCK    : in std_logic;

    -- From PLL Serial Inteface
    PLL_TX_END  : in std_logic;  -- Status of serial transmission

    -- From/to Decoders
    RTS0_A      : in std_logic;         
    RTS0_B      : in std_logic;

    -- LED control signals
    LED         : out std_logic_vector(7 downto 0);  -- LED control

    -- GPIOs
    GPIO        : inout std_logic_vector(7 downto 0);  -- GPIOs

    -- Flash signals
    FLASH_PAGEz : out std_logic_vector(2 downto 0);  -- Paging for Flash

    -- UART signals
    UART_INTA   : in std_logic;  -- Interrupt from UART A
    UART_INTB   : in std_logic   -- Interrupt from UART B
    );
end REG;

architecture RTL of REG is

signal P_LED : std_logic_vector(7 downto 0); -- LED control signals
signal P_FLASH_PAGEz : std_logic_vector(2 downto 0); -- Flash pages
signal P_FLASH_ACC : std_logic; -- Flash accelerator control
signal P_INT_MASK : std_logic_vector(4 downto 0); -- Interrupt mask
signal RST, P_SRESETz : std_logic; -- Soft reset
signal P_PIXEL_CNT : std_logic_vector(11 downto 0); -- Pixel count per DMA
signal P_OSD_EN : std_logic; -- OSD enable
signal P_INTEN : std_logic; -- Interrupts enable
signal GPIO_DIR : std_logic_vector(7 downto 0); -- GPIOs direction
signal GPIO_REG : std_logic_vector(7 downto 0); -- GPIOs register
signal GPIO_READ : std_logic_vector(7 downto 0); -- GPIOs values read
signal S_UART_INTA, S_UART_INTB : std_logic; -- synchronized uart interrupts
signal UARTA_INTEN, UARTB_INTEN : std_logic; -- UART interrupt enables
signal S_RTS0_A, S_RTS0_B : std_logic; -- synchronized decoder interrupts
signal RTS0A_INTEN, RTS0B_INTEN : std_logic; -- Decoder interrupt enable
signal S_FIFO_URUN : std_logic;       -- synchronized FIFO underrun
signal L1_FIFO_URUN : std_logic;        -- FIFO underrun with latency 1
signal URUN_INTEN : std_logic;        -- FIFO underrun interrupt enable
signal P_BUS_WIDTH_8 : std_logic;
signal P_CLEAR_CLUT : std_logic;
signal PLL_TX_END_FLAG : std_logic;    -- flag for PLL transmit complete
signal PLL_FLAG_RST : std_logic;      -- Reset for PLL flag
signal L1_PLL_TX_END : std_logic;
signal L1_REG_DSz : std_logic;          -- pipelined data strobe
signal P_DLL_RST : std_logic;           -- DLL reset bit
signal S_DLL_LOCK : std_logic;          -- DLL lock status

begin	-- RTL

        
    -- purpose: writing to soft reset bit in control register
    RST_BIT: process (EMIF_CLK, RESETz)
    begin  -- process RST_BIT
        if RESETz = '0' then  -- asynchronous reset (active low)
            RST <= '0';
        elsif EMIF_CLK'event and EMIF_CLK = '1' then  -- rising clock edge
            if REG_CSlz = '0' and REG_DSz = '0' and REG_RWz = '0'
                and ADDRb(3 downto 0) = "0000" then
                RST <= DATA_INb(0);
            end if;
        end if;
    end process RST_BIT;


    -- purpose: generate soft reset
    SFT_RST: process (EMIF_CLK, RESETz)
    begin  -- process SFT_RST
        if RESETz = '0' then  -- asynchronous reset (active low)
            P_SRESETz <= '0';
        elsif EMIF_CLK'event and EMIF_CLK = '1' then  -- rising clock edge
            if RST = '1' then
                P_SRESETz <= '0';
            else
                P_SRESETz <= '1';
            end if;
        end if;
    end process SFT_RST;
  
    -- purpose: This process writes to asynchronous registers
    REG_WRITE: process(EMIF_CLK, RESETz)
    begin 

        if RESETz = '0' or P_SRESETz = '0' then
            P_PIXEL_CNT <= (others => '0');
            GPIO_DIR <= (others => '0');
            GPIO_REG <= (others => '0');
            P_LED <= (others => '0');
            P_FLASH_PAGEz <= (others => '0');
            P_INT_MASK <= (others => '0');
            P_OSD_EN <= '0';
            P_INTEN <= '0';
            P_BUS_WIDTH_8 <= '1';
            P_CLEAR_CLUT <= '0';
            P_DLL_RST <= '0';
        elsif EMIF_CLK'event and EMIF_CLK = '1' then
            if REG_CSlz = '0' and REG_DSz = '0' and REG_RWz = '0' then
                case ADDRb(3 downto 0) is
                    when "0000" =>
                        P_OSD_EN <= DATA_INb(1);
                        P_INTEN <= DATA_INb(2);
                        P_BUS_WIDTH_8 <= DATA_INb(3);
                        P_CLEAR_CLUT <= DATA_INb(4);
                        P_DLL_RST <= DATA_INb(5);
                    when "0001" =>
                        P_PIXEL_CNT(7 downto 0) <= DATA_INb(7 downto 0);
                    when "0010" =>
                        P_PIXEL_CNT(11 downto 8) <= DATA_INb(3 downto 0);
                    when "0100" =>
                        P_INT_MASK <= DATA_INb(4 downto 0);
                    when "0101" =>
                        GPIO_DIR <= DATA_INb(7 downto 0);
                    when "0110" =>
                        GPIO_REG <= DATA_INb(7 downto 0);
                    when "0111" =>
                        P_LED <= DATA_INb(7 downto 0);
                    when "1000" =>
                        P_FLASH_PAGEz <= DATA_INb(2 downto 0);
                    when others =>
                        null;
                end case;
            end if;
        end if;
    end process REG_WRITE;