osd_mux.vhd

TI evm642的源码,给那些没有买TI的评估板,却想要评估板程序的人.

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-- *** Disclaimer: This example code is provided with no support. ***
------------------------------------------------------------------------------
-- File          : osd_mux.vhd
-- Author        : Shraddha
-- Created       : 
-- Last modified : April 25, 2003
-- Project	 : OSD FPGA
------------------------------------------------------------------------------
-- Description : Multiplexes Video and OSD data
-- 
------------------------------------------------------------------------------
-- Modification history :
-- Jan 13, 2003 : Shraddha : created
-- April 25, 2003 : Shraddha: Added soft reset to the module
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity OSD_MUX is
port (
    -- from Power Supply
    RESETz              : in std_logic;  -- System Reset
    SRESETz             : in std_logic;  -- Soft reset
    
    -- Clock
    VCLK                : in std_logic;  -- Video Clock
    
    -- From CLUT
    OSD_DATA            : in std_logic_vector(15 downto 0);  -- OSD data
    ALPHA_LSB           : in std_logic;  -- Alpha for LSB
    ALPHA_MSB           : in std_logic;  -- Alpha for MSB

    -- From Video I/F
    VIDEO_DATA          : in std_logic_vector(19 downto 0);  -- Video Data

    -- From State machine
    MUX_CTL             : in std_logic;  -- Control for the multiplexer

    -- To Video Output Module
    VID_OSD_DATA        : out std_logic_vector(19 downto 0)  -- Multiplexed data
    );
end OSD_MUX;

architecture RTL of OSD_MUX is

signal L1_MUX_CTL : std_logic;
signal MSB_LSB : std_logic;
signal L1_ALPHA_LSB, L1_ALPHA_MSB : std_logic;
signal P_VID_OSD_DATA : std_logic_vector(19 downto 0);
  
begin	-- RTL

  -- purpose: Multiplexes Video and OSD data
  MUX: process (VCLK, RESETz)
  begin  -- process MUX
    if RESETz = '0' or SRESETz = '0' then   --asynchronous reset (active low)
      P_VID_OSD_DATA <= (others => '0');
    elsif VCLK'event and VCLK = '1' then  -- rising clock edge
        -- The Video LSB data is multiplexed with OSD LSB data.  MUX_CTL is
        -- signal that comes from the OSD_SM. If this is high, and if the
        -- alpha for LSB data is high then the OSD data is outputted from the
        -- multiplexer.  Otherwise, Video data is outputted.
        if MUX_CTL = '1' and ALPHA_LSB = '1' then
          P_VID_OSD_DATA(9 downto 2) <= OSD_DATA(7 downto 0);
        else
          P_VID_OSD_DATA(9 downto 2) <= VIDEO_DATA(9 downto 2);
        end if;
        P_VID_OSD_DATA(1 downto 0) <= VIDEO_DATA(1 downto 0);

        -- The Video MSB data is multiplexed with OSD MSB data.  MUX_CTL is
        -- signal that comes from the OSD_SM.  If this is high, and if the
        -- alpha for MSB data is high then then OSD data is outputted from the
        -- multiplexer.  Otherwise, video data is outputted.
        if MUX_CTL = '1' and ALPHA_MSB = '1' then
          P_VID_OSD_DATA(19 downto 12) <= OSD_DATA(15 downto 8);
        else
          P_VID_OSD_DATA(19 downto 12) <= VIDEO_DATA(19 downto 12);
        end if;
        P_VID_OSD_DATA(11 downto 10) <= VIDEO_DATA(11 downto 10);
    end if;
  end process MUX;

  
  VID_OSD_DATA <= P_VID_OSD_DATA;
  
end RTL;