emif_if.vhd

TI evm642的源码,给那些没有买TI的评估板,却想要评估板程序的人.

------------------------------------------------------------------------------
-- *** Disclaimer: This example code is provided with no support. ***
------------------------------------------------------------------------------
-- File          : emif_if.vhd
-- Author        : Shraddha
-- Created       : 
-- Last modified : June 20, 2003
-- Project	 : Interfacing EMIF to OSD FPGA
------------------------------------------------------------------------------
-- Description :
-- This module interfaces to the DM642 EMIF and provides appropriate signals
-- to reg and sync_reg and fifo modules.
------------------------------------------------------------------------------
-- Modification history :
-- Jan 02, 2003 : Shraddha : created
-- June 20, 2003 : Shraddha : Removed UART chip select logic from the design.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity EMIF_IF is
port (
    -- from Power Supply
    RESETz              : in std_logic;  -- System Reset
    
    -- Clocky
    EMIF_CLK            : in std_logic;  -- 100 Mhz EMIF Clock

    -- from/to C64x
    DM642_AOE_SOEz      : in std_logic;  -- Output Enable
    DM642_ARE_SREz      : in std_logic;  -- Read enable
    DM642_AWE_SWEz      : in std_logic;  -- Write Enable
    DM642_CE1z          : in std_logic;  -- CE1 select
    DM642_CE2z          : in std_logic;  -- CE2 select
    DM642_CE3z          : in std_logic;  -- CE3 select
    DM642_EA_22         : in std_logic;  -- DM642 address
    DM642_EA            : in std_logic_vector(4 downto 0);
    DM642_DATAbt        : inout std_logic_vector(31 downto 0);  -- DM642 Data 

    -- signals from/to asynchronous reg module
    REG_CSlz            : out std_logic;  -- Chip select for Registers
    REG_DSz             : out std_logic;  -- Data strobe for read/write
    REG_RWz             : out std_logic;  -- Register read/write select
    REG_ADDRb           : out std_logic_vector(3 downto 0); -- Register address
    REG_DATA_INb        : out std_logic_vector(7 downto 0);  -- Register data
                                                              -- in
    REG_DATA_OUTb       : in std_logic_vector(7 downto 0);  -- Register data
    
    -- signals from/to synchronous reg module
    SYNC_REG_CSlz       : out std_logic; -- Chip select for Sync Registers
    SREz                : out std_logic; -- Read enable for Sync Registers
    SWEz                : out std_logic; -- Write enable for Sync Registers
    SOEz                : out std_logic; -- Output enable for Sync Registers
    SADDRb              : out std_logic_vector(4 downto 0); -- Address
    SADDRb_22           : out std_logic; -- Address bit 22
    SREG_DATA_INb       : out std_logic_vector(31 downto 0); -- Data in
    SREG_DATA_OUTb      : in std_logic_vector(31 downto 0); -- Data out

    -- signals to fifo module
    FIFO_WE             : out std_logic;  -- Write Enable for FIFO
    FIFO_DATA_INb       : out std_logic_vector(31 downto 0);  -- FIFO data in

    -- signals for CLUT module
    CLUT_WE             : out std_logic;  -- Write enable for CLUT
    CLUT_DATA_INb       : out std_logic_vector(23 downto 0);  -- CLUT data in

    -- Transceiver controls
    DC_EMIF_OEz : out std_logic;
    DC_EMIF_DIR : out std_logic
    );
end EMIF_IF;

architecture RTL of EMIF_IF is
  
signal L1_EA_22 : std_logic;  -- registered address
signal L1_EA : std_logic_vector(4 downto 0);
signal DATA_INb : std_logic_vector(31 downto 0);  -- registered data
signal ASYNC_CSz : std_logic;           -- registered asynchronous chip select
signal SYNC_CSz : std_logic;            -- registered synchronous chip select
signal AOE_SOEz : std_logic;            -- registered output enable
signal ARE_SREz : std_logic;            -- registered read enable
signal AWE_SWEz : std_logic;            -- registered write enable
signal P_REG_CSlz : std_logic; 			-- Asynch registers chip select
signal SREG_CSlz : std_logic;  		-- Synchronous registers chip select

begin	-- RTL

  -- purpose: Pipeline signals coming from DM642.  Registering all the signals
  -- coming in helps with meeting setup time.
  PIPELINE: process (EMIF_CLK, RESETz)
  begin  -- process PIPELINE
    if RESETz = '0' then                -- asynchronous reset (active low)
      L1_EA <= (others => '0');
      L1_EA_22 <= '0';
      DATA_INb <= (others => '0');
      ASYNC_CSz <= '1';
      SYNC_CSz <= '1';
      AOE_SOEz <= '1';
      ARE_SREz <= '1';
      AWE_SWEz <= '1';
     elsif EMIF_CLK'event and EMIF_CLK = '1' then  -- rising clock edge
      L1_EA <= DM642_EA;
      L1_EA_22 <= DM642_EA_22;
      DATA_INb <= DM642_DATAbt;
      SYNC_CSz <= DM642_CE3z;
      ASYNC_CSz <= DM642_CE1z;
      AOE_SOEz <= DM642_AOE_SOEz;
      ARE_SREz <= DM642_ARE_SREz;
      AWE_SWEz <= DM642_AWE_SWEz;
    end if;
  end process PIPELINE;

  -- purpose: Generates control signals for Register read/write in asynchronous space
  ASYNC_CTL: process (EMIF_CLK, RESETz)
  begin  -- process ASYNC_CTL
    if RESETz = '0' then                -- asynchronous reset (active low)
      P_REG_CSlz <= '1';
      REG_DSz <= '1';
      REG_RWz <= '0';
      REG_ADDRb <= (others => '0');
      REG_DATA_INb <= (others => '0');
    elsif EMIF_CLK'event and EMIF_CLK = '1' then  -- rising clock edge
        -- When EA(22) is '0' that is Flash address space
        -- When EA(22) is '1' it is UART and Asychrnous registers address space
      if ((ASYNC_CSz = '0') and (L1_EA_22 = '1')) then
 	   if (L1_EA(4) = '1') then
		P_REG_CSlz <= '0';
	   else
		  P_REG_CSlz <= '1';
  	   end if;
      else
        P_REG_CSlz <= '1';
      end if;
      
      if ((ARE_SREz = '0') or (AWE_SWEz = '0')) then
        REG_DSz <= '0';
      else
        REG_DSz <= '1';
      end if;

      REG_RWz <= not AOE_SOEz;

      REG_ADDRb <= L1_EA(3 downto 0);

      REG_DATA_INb <= DATA_INb(7 downto 0);
    end if;
  end process ASYNC_CTL;

  -- purpose: Generates control signals for synchronous space
  SYNC_CTL: process (EMIF_CLK, RESETz)
  begin  -- process SYNC_CTL
    if RESETz = '0' then                -- asynchronous reset (active low)
      FIFO_WE <= '0';
      FIFO_DATA_INb <= (others => '0');
      CLUT_WE <= '0';
      CLUT_DATA_INb <= (others => '0');
      SREG_CSlz <= '1';
    elsif EMIF_CLK'event and EMIF_CLK = '1' then  -- rising clock edge
      FIFO_WE <= '0';
      CLUT_WE <= '0';
      -- When EA(22) is '0' it is FPGA's synchrounous space for registers and FIFOs
      -- When EA(22) is '1' address space is open for any other use
      if (SYNC_CSz = '0') and (AWE_SWEz = '0') and L1_EA_22 = '0' and L1_EA(4) = '1' then
         case L1_EA(3 downto 0) is
          	when "0000" =>
            FIFO_WE <= '1';
            FIFO_DATA_INb <= DATA_INb;
          	when "0001" =>
            CLUT_WE <= '1';
            CLUT_DATA_INb <= DATA_INb(23 downto 0);
          	when others =>
            null;
        end case;
      end if;

      -- The SREG_CSlz signals is generated only to control the tristate Data
      -- bus.  The actual logic for chip select used for synchronous registers
      -- is in the SYNC_REG module.  The registered CE3z is passed to this
      -- module  for this purpose.
      if SYNC_CSz = '0' and L1_EA_22 = '0' and L1_EA(4) = '0' then
      	SREG_CSlz <= '0';
      else
      	SREG_CSlz <= '1';
      end if;
    end if;
  end process SYNC_CTL;

  -- Data bus tristate control
  -- Though the synchronous register read logic is implemented here, when the
  -- EMIF is run at 133MHz, the reading of these registers is not reliable.
  -- The reading is reliable at 66Mhz.
  DM642_DATAbt(7 downto 0) <= REG_DATA_OUTb when P_REG_CSlz = '0' and AOE_SOEz = '0' else
  			SREG_DATA_OUTb(7 downto 0)	when SREG_CSlz = '0' and AOE_SOEz = '0' else
                       (others => 'Z');

  DM642_DATAbt(31 downto 8) <= SREG_DATA_OUTb(31 downto 8) when SREG_CSlz = '0' and AOE_SOEz = '0' else
  			(others => 'Z');

  -- Transceivers control
  -- The output enable for the transceivers in the path of Daughter cards and
  -- the FPGA is asserted when any of the three CE space enable signals are
  -- asserted.  The transceiver direction signal is derived straight from the
  -- DM642_AOE_SOEz signal.  For the EVM the DSP is on the B port of the
  -- transceivers and the FPGA and daughter cards on the A port.  The
  -- direction signal is active high.

  DC_EMIF_OEz <= '0' when DM642_CE1z = '0' or DM642_CE2z = '0'
                 or DM642_CE3z = '0' else
                 '1';

  DC_EMIF_DIR <= not DM642_AOE_SOEz;

  REG_CSlz <= P_REG_CSlz;  
  SYNC_REG_CSlz <= SYNC_CSz;
  SWEz <= AWE_SWEz;
  SREz <= ARE_SREz;
  SOEz <= AOE_SOEz;
  SREG_DATA_INb <= DATA_INb;
  SADDRb <= L1_EA(4 downto 0);
  SADDRb_22 <= L1_EA_22;
        
end RTL;