hd_ddr.vhd

TI evm642的源码,给那些没有买TI的评估板,却想要评估板程序的人.

------------------------------------------------------------------------------
-- *** Disclaimer: This example code is provided with no support. ***
------------------------------------------------------------------------------
-- File          : hd_ddr.vhd
-- Author        : Shraddha
-- Created       : 
-- Last modified : Jan 09, 2003
-- Project	 : OSD FPGA
------------------------------------------------------------------------------
-- Description : This module encodes the data as dual clock edge data.  Dual
-- clock edged data is needed to satisfy HD and VGA modes.  It is also useful
-- for other video port modes.  However 8-bit BT656 mode does not need dual
-- clock edged data.  This module looks at the BUS width signal to find out
-- whether dual clock edging is required.  Since the module always performs
-- dual clock edging whether it is required or not, for those cases where it
-- is not needed, the module replicates LSB databus on the MSB databus and
-- then  performs dual clock edging funtion.  This ensures that the data will
-- change only once per clock period.
-- 
------------------------------------------------------------------------------
-- Modification history :
-- Jan 09, 2003 : Shraddha : created
-- April 25, 2003 : Shraddha: Added soft reset to the module
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity HD_DDR is
port (
    -- from Power Supply
    RESETz      : in std_logic;  -- System Reset
    SRESETz     : in std_logic;  -- Soft Reset
    
    -- Clock
    VCLK        : in std_logic;  -- Video Clock
    VCLK_90     : in std_logic;  -- Video clock phase shift 90

    -- From registers
    BUS_WIDTH_8 : in std_logic;

    -- from/to OSD mux
    VID_OSD_DATA : in std_logic_vector(19 downto 0);  

    -- To encoder
    PIXCLKI     : out std_logic;
    DENCDATA    : out std_logic_vector(11 downto 0)
    );
end HD_DDR;

architecture RTL of HD_DDR is

component DDRFD
    port (
        DR      : in  std_logic;
        DF      : in std_logic;
        C       : in std_logic;
        RST     : in std_logic;
        Q       : out std_logic
        );
end component;

signal ENCODER_DATA : std_logic_vector(19 downto 0);
signal DENCDATA_RISING : std_logic_vector(7 downto 0);
signal DENCDATA_FALLING : std_logic_vector(7 downto 0);
signal L1_VID_OSD_DATA : std_logic_vector(19 downto 0);
signal RESET : std_logic;
signal tied_high, tied_low : std_logic;
  
begin	-- RTL

  -- The LSB encoder data is always the LSB data from the OSD MUX.
  ENCODER_DATA(9 downto 0) <= VID_OSD_DATA(9 downto 0);

  -- The MSB encoder data is LSB data from the OSD MUX (with one clock latency
  -- to line up correctly in the pipeline) when the bus width is 8 bits and no
  -- dual clock edging is required.  The MSB encoder data is MSB data from the
  -- OSD mux if the bus width is 16 bits and dual clock edging is required.
  ENCODER_DATA(19 downto 10) <= L1_VID_OSD_DATA(9 downto 0) when BUS_WIDTH_8 = '1' else
                                VID_OSD_DATA(19 downto 10);

  -- purpose: Add Latency
  LATENCY : process (VCLK, RESETz)
  begin  -- process LATENCY
    if RESETz = '0' or SRESETz = '0' then  -- asynchronous reset (active low)
      DENCDATA_RISING <= (others => '0');
      DENCDATA_FALLING <= ( others => '0');
      L1_VID_OSD_DATA <= ( others => '0');
    elsif VCLK'event and VCLK = '1' then  -- rising clock edge
      DENCDATA_RISING(7 downto 0) <= ENCODER_DATA(9 downto 2);
      DENCDATA_FALLING(7 downto 0) <= ENCODER_DATA(19 downto 12);
      L1_VID_OSD_DATA <= VID_OSD_DATA;
    end if;
  end process LATENCY;


  DENCDATA(11 downto 8) <= (others => '0');
  tied_low <= '0';
  tied_high <= '1';

  -- These component instantiations implement dual clock edging with a hard
  -- macro to help meet timings.
  DDR0 : DDRFD
      port map(
        DR      => DENCDATA_RISING(0),
        DF      => DENCDATA_FALLING(0),
        C       => VCLK,
        RST     => RESET,
        Q       => DENCDATA(0)
        );
  
  DDR1 : DDRFD
      port map(
        DR      => DENCDATA_RISING(1),
        DF      => DENCDATA_FALLING(1),
        C       => VCLK,
        RST     => RESET,
        Q       => DENCDATA(1)
        );
 
  DDR2 : DDRFD
      port map(
        DR      => DENCDATA_RISING(2),
        DF      => DENCDATA_FALLING(2),
        C       => VCLK,
        RST     => RESET,
        Q       => DENCDATA(2)
        );
 
  DDR3 : DDRFD
      port map(
        DR      => DENCDATA_RISING(3),
        DF      => DENCDATA_FALLING(3),
        C       => VCLK,
        RST     => RESET,
        Q       => DENCDATA(3)
        );
 
  DDR4 : DDRFD
      port map(
        DR      => DENCDATA_RISING(4),
        DF      => DENCDATA_FALLING(4),
        C       => VCLK,
        RST     => RESET,
        Q       => DENCDATA(4)
        );
 
   DDR5 : DDRFD
      port map(
        DR      => DENCDATA_RISING(5),
        DF      => DENCDATA_FALLING(5),
        C       => VCLK,
        RST     => RESET,
        Q       => DENCDATA(5)
        );
 
  DDR6 : DDRFD
      port map(
        DR      => DENCDATA_RISING(6),
        DF      => DENCDATA_FALLING(6),
        C       => VCLK,
        RST     => RESET,
        Q       => DENCDATA(6)
        );
 
  DDR7 : DDRFD
      port map(
        DR      => DENCDATA_RISING(7),
        DF      => DENCDATA_FALLING(7),
        C       => VCLK,
        RST     => RESET,
        Q       => DENCDATA(7)
        );

  -- To help meet the hold time requirements of the Encoder, the 90 degrees
  -- phase shifted clock is passed through a similar dual clock edging module.
  --  The similar hard macro ensures that the delay path for the clock inside
  --  the FPGA is same as that for the data.  The 90 degrees phase shift input
  --  to this module ensures that the clock will transition in center of the
  --  data transitions for the dual clock edged data.
  DDRCLK : DDRFD
      port map(
        DR      => tied_high,
        DF      => tied_low,
        C       => VCLK_90,
        RST     => RESET,
        Q       => PIXCLKI
        );


RESET <= not SRESETz;
 
   
end RTL;