sync_reg.vhd

TI evm642的源码,给那些没有买TI的评估板,却想要评估板程序的人.

------------------------------------------------------------------------------
-- *** Disclaimer: This example code is provided with no support. ***
------------------------------------------------------------------------------
-- File          : sync_reg.vhd
-- Author        : Shraddha
-- Created       : 
-- Last modified : June 12, 2003
-- Project	 : OSD FPGA
------------------------------------------------------------------------------
-- Description :
-- This is the Synchronous registers module.
------------------------------------------------------------------------------
-- Modification history :
-- Feb 05, 2003 : Shraddha : created
-- June 12, 2003: Shraddha : added OSD_XSTART, OSD_YSTART, OSD_XSTOP,
-- OSD_YSTOP and EVTS_PER_FIELD registers to the design.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity SYNC_REG is
port (
    -- from Power Supply
    RESETz      : in std_logic;  -- System Reset
    SRESETz     : in std_logic;  -- Soft Reset
    
    -- Clock
    EMIF_CLK    : in std_logic;  -- 100 Mhz EMIF Clock

    -- from/to EMIF IF
    SYNC_REG_CSlz : in std_logic;       -- Sync chip select
    SREz        : in std_logic;  -- Read enable
    SWEz        : in std_logic;         -- Write enable
    SOEz        : in std_logic;         -- Output enable
    SADDRb      : in std_logic_vector(4 downto 0);  -- Address
    SADDRb_22   : in std_logic;         -- Address bit 22
    SREG_DATA_INb : in std_logic_vector(31 downto 0);  -- Data in
    SREG_DATA_OUTb : out std_logic_vector(31 downto 0);  -- Data out
    
    -- To OSD_SM
    OSD_XSTART 	: out std_logic_vector(11 downto 0); -- OSD xstart pixel
    OSD_YSTART	: out std_logic_vector(11 downto 0); -- OSD ystart line
    OSD_XSTOP 	: out std_logic_vector(11 downto 0); -- OSD xstop pixel
    OSD_YSTOP 	: out std_logic_vector(11 downto 0); -- OSD ystop line
    EVTS_PER_FIELD : out std_logic_vector(15 downto 0); -- Events per field

    -- To PLL_SI
    PLL_TX_DATA : out std_logic_vector(15 downto 0);
    PLL_TX_START : out std_logic
    );
end SYNC_REG;

architecture RTL of SYNC_REG is
    
signal P_PLL_TX_DATA : std_logic_vector(15 downto 0); -- PLL config data
signal P_PLL_TX_START : std_logic; -- starts serial transmission to PLL
signal P_TEST_REG : std_logic_vector(31 downto 0);
signal SREG_WEz : std_logic;
signal L1_SREG_DATA_INb : std_logic_vector(31 downto 0);
signal L1_SADDRb : std_logic_vector(4 downto 0);
signal P_OSD_XSTART : std_logic_vector(11 downto 0);
signal P_OSD_YSTART : std_logic_vector(11 downto 0);
signal P_OSD_XSTOP : std_logic_vector(11 downto 0);
signal P_OSD_YSTOP : std_logic_vector(11 downto 0);
signal P_EVTS_PER_FIELD : std_logic_vector(15 downto 0);

  
begin	-- RTL

        
-------------------------------------------------------------------------------
--  SYNC Register READ/WRITE
-------------------------------------------------------------------------------
  
  -- purpose: This process generates chip selects tow write to registers
  SREG_WCTL: process(EMIF_CLK, RESETz)
  begin 

    if RESETz = '0' or SRESETz = '0' then
        SREG_WEz <= '1';
        L1_SREG_DATA_INb <= (others => '0');
        L1_SADDRb <= (others => '0');
    elsif EMIF_CLK'event and EMIF_CLK = '1' then
      if SYNC_REG_CSlz = '0' and SADDRb(4) = '0' and SADDRb_22 = '0' and
          SWEz = '0' and SREz = '1' and SOEz = '1' then
          SREG_WEz <= '0';
      else
          SREG_WEz <= '1';
      end if;
      L1_SREG_DATA_INb <= SREG_DATA_INb;
      L1_SADDRb <= SADDRb;
    end if;
  end process SREG_WCTL;
	
  -- purpose: This process writes to registers
  SREG_WRITE: process(EMIF_CLK, RESETz)
  begin 

    if RESETz = '0' or SRESETz = '0' then
      P_PLL_TX_DATA <= (others => '0');
      P_PLL_TX_START <= '0';
      P_TEST_REG <= ( others => '0');
      P_OSD_XSTART <= (others => '0');
      P_OSD_YSTART <= (others => '0');
      P_OSD_XSTOP <= (others => '1');
      P_OSD_YSTOP <= (others => '1');
      P_EVTS_PER_FIELD <= (others => '0');
    elsif EMIF_CLK'event and EMIF_CLK = '1' then
      P_PLL_TX_START <= '0';
      if SREG_WEz = '0' then
        case L1_SADDRb(3 downto 0) is
          when "0000" =>
              P_TEST_REG <= L1_SREG_DATA_INb;
          when "0001" =>
              P_PLL_TX_DATA(15 downto 0) <= L1_SREG_DATA_INb(15 downto 0);
              P_PLL_TX_START <= '1';
	  when "0010" =>
	      P_OSD_XSTART(11 downto 0) <= L1_SREG_DATA_INb(11 downto 0);
	  when "0011" =>
	      P_OSD_YSTART(11 downto 0) <= L1_SREG_DATA_INb(11 downto 0);
 	  when "0100" =>
	      P_OSD_XSTOP(11 downto 0) <= L1_SREG_DATA_INb(11 downto 0);
 	  when "0101" =>
	      P_OSD_YSTOP(11 downto 0) <= L1_SREG_DATA_INb(11 downto 0);
	  when "0110" =>
	      P_EVTS_PER_FIELD <= L1_SREG_DATA_INb(15 downto 0);
           when others =>
            null;
        end case;
      end if;
    end if;
  end process SREG_WRITE;
		
  -- purpose: This process reads from registers
  SREG_READ: process(EMIF_CLK, RESETz)
  begin
    
    if RESETz = '0' or SRESETz = '0' then
      SREG_DATA_OUTb <= (others => '0');
    elsif EMIF_CLK'event and EMIF_CLK = '1' then
      SREG_DATA_OUTb <= (others => '0');
      case SADDRb(3 downto 0) is
        when "0000" =>
            SREG_DATA_OUTb(31 downto 0) <= P_TEST_REG;
        when "0001" =>
            SREG_DATA_OUTb(15 downto 0) <= P_PLL_TX_DATA(15 downto 0);
	when "0010" =>
		SREG_DATA_OUTb(11 downto 0) <= P_OSD_XSTART;
	when "0011" =>
		SREG_DATA_OUTb(11 downto 0) <= P_OSD_YSTART;
	when "0100" =>
		SREG_DATA_OUTb(11 downto 0) <= P_OSD_XSTOP;
	when "0101" =>
		SREG_DATA_OUTb(11 downto 0) <= P_OSD_YSTOP;
	when "0110" =>
		SREG_DATA_OUTb(15 downto 0) <= P_EVTS_PER_FIELD;
        when others =>
            SREG_DATA_OUTb <= (others => '0');
      end case;
    end if;
  end process SREG_READ;

  PLL_TX_DATA <= P_PLL_TX_DATA;
  PLL_TX_START <= P_PLL_TX_START;
OSD_XSTART <= P_OSD_XSTART;
OSD_YSTART <= P_OSD_YSTART;
OSD_XSTOP <= P_OSD_XSTOP;
OSD_YSTOP <= P_OSD_YSTOP;
EVTS_PER_FIELD <= P_EVTS_PER_FIELD;

 
end RTL;