osd_sm.vhd

TI evm642的源码,给那些没有买TI的评估板,却想要评估板程序的人.

------------------------------------------------------------------------------
-- *** Disclaimer: This example code is provided with no support. ***
------------------------------------------------------------------------------
-- File          : osd_sm.vhd
-- Author        : Shraddha
-- Created       : 
-- Last modified : 06/16/03
-- Project	 : OSD FPGA
------------------------------------------------------------------------------
-- Description : This module has the OSD state machine that controls the OSD
-- and Video functionality of the OSD FPGA.
-- 
------------------------------------------------------------------------------
-- Modification history :
-- Jan 9th, 2003 : Shraddha : created
-- June 16th, 2003 : Shraddha : The OSD requirements were changed to include a
-- OSD window.  The state machine was changed accordingly.  Now the MUX_CTL
-- is governed by OSD window parameters as well as the active video signal.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity OSD_SM is
port (
    -- from Power Supply
    RESETz              : in std_logic;  -- System Reset
    SRESETz             : in std_logic;  -- Soft Reset
    
    -- Clock
    VCLK               : in std_logic;  -- Video Clock
    
    -- Video Port controls
    AVID                : in std_logic; -- Active Video
    VSYNC               : in std_logic; -- Vertical Sync
    HSYNC 			: in std_logic; -- Horizontal sync

    -- from/to registers
    OSD_EN              : in std_logic;  -- Enable OSD
    BUS_WIDTH_8 			: in std_logic; -- Video port bus width
    OSD_XSTART			: in std_logic_vector(11 downto 0); -- OSD xstart pixel
    OSD_YSTART 			: in std_logic_vector(11 downto 0); -- OSD ystart pixel
    OSD_XSTOP 			: in std_logic_vector(11 downto 0); -- OSD xtop pixel
    OSD_YSTOP			: in std_logic_vector(11 downto 0); -- OSD ystop pixel
    FIFO_URUN           : out std_logic;  -- FIFO underrun indicator

    -- from FIFO
    FIFO_EMPTY          : in std_logic;   -- OSD FIFO is empty

    -- To dma event generator
    EVT_EN              : out std_logic;  -- Enable DMA events

    -- To FIFOs
    FLUSH_FIFO          : out std_logic;  -- Flush FIFOs

    -- To Unpack module
    DATA_UNPACK         : out std_logic;  -- Unpack data indicator

    -- To Mux module
    MUX_CTL             : out std_logic  -- OSD/Video mux control

    );
end OSD_SM;

architecture RTL of OSD_SM is

type STATE_TYPE is (
  IDLE,           -- This is where the state machine idles
  INITIAlIZE,     -- All parameters are initialized here
  ACTIVE_VIDEO,   -- Active Video state
  BLANKING        -- Blanking state
  );    
signal PRESENT_STATE, NEXT_STATE : STATE_TYPE;


signal N_EVT_EN : std_logic; -- Event enable transitional variable
signal P_EVT_EN : std_logic; -- Event enable
signal N_MUX_CTL : std_logic; -- mux control transitional variable
signal P_MUX_CTL : std_logic; -- mux control
signal E5_MUX_CTL : std_logic; -- mux control, latency=-5
signal E4_MUX_CTL : std_logic; -- mux control, latency=-4
signal E3_MUX_CTL : std_logic; -- mux control, latency=-3
signal E2_MUX_CTL : std_logic; -- mux control, latency=-2
signal E1_MUX_CTL : std_logic; -- mux control, latency=-1
signal P_DATA_UNPACK : std_logic; -- Data unpack indicator
signal N_DATA_UNPACK : std_logic; -- Data unpack indicator transitional variable 
signal N_FIFO_FLUSH : std_logic; -- FIFO Flush, transitional variable
signal FIFO_FLUSH : std_logic;   -- FIFO Flush indicator
signal L1_OSD_EN : std_logic;    -- pipelined osd enable
signal N_ACTIVE_CTL : std_logic; -- mux control state during active
                                 -- video, transitional variable
signal ACTIVE_CTL : std_logic;   -- mux control state during active video
signal NEW_FIELD : std_logic;    -- indicates new field has started
signal N_NEW_FIELD : std_logic;  -- new field transitional variable
signal P_FIFO_URUN : std_logic;  -- indicates FIFO underrun
signal N_FIFO_URUN : std_logic;  -- fifo underrun, transitional variable
signal L_OSD_XSTART : std_logic_vector(11 downto 0); -- latched osd xstart pixel
signal N_L_OSD_XSTART : std_logic_vector(11 downto 0); -- latched osd xstart pixel transitional variable
signal L_OSD_YSTART : std_logic_vector(11 downto 0); -- latched osd ystart pixel
signal N_L_OSD_YSTART : std_logic_vector(11 downto 0); -- latched osd ystart pixel transitional variable
signal L_OSD_XSTOP : std_logic_vector(11 downto 0); -- latched osd xstop pixel
signal N_L_OSD_XSTOP : std_logic_vector(11 downto 0); -- latched osd xstop pixel transitional variable
signal L_OSD_YSTOP : std_logic_vector(11 downto 0); -- latched osd ystop pixel
signal N_L_OSD_YSTOP : std_logic_vector(11 downto 0); -- latched osd ystop pixel transitional variable
signal FIELD_SET : std_logic; -- field detection has set the field
signal N_FIELD_SET : std_logic; -- field detection has set the field transitional variable
signal FIELD : std_logic; -- field '0' is field 1 and '1' is field 2
signal N_FIELD : std_logic; -- field '0' is field 1 and '1' is field 2 transitional variable
signal DETECT_CNTR : std_logic_vector(6 downto 0); -- field detection counter
signal N_DETECT_CNTR : std_logic_vector(5 downto 0); -- field detection counter transitional variable
signal CNTR_ON : std_logic; -- counter for field detection is on
signal N_CNTR_ON : std_logic; -- counter for field detection is on transitional variable
signal L1_VSYNC, L1_HSYNC : std_logic; -- sync signals, latency = 1
signal FP_COUNT : std_logic_vector(11 downto 0); -- active pixel count
signal FL_COUNT : std_logic_vector(11 downto 0); -- active line count
signal DETECT_VSYNC : std_logic; -- VSYNC detected during field detection
signal N_DETECT_VSYNC : std_logic; -- VSYNC detected during field detection transitional variable
signal OSD_START : std_logic; -- Signal goes high in Field 1 to make sure OSD starts with field 1
signal N_OSd_START : std_logic; -- transitional variable
signal FL_COUNT_RESET : std_logic;
signal COUNT_EN : std_logic; -- used when bus width is 8
constant VID_DATA : std_logic := '0';
constant OSD_DATA : std_logic := '1';


begin	-- RTL

  -- purpose: This process controls the states in the state machine.
  SM : process(PRESENT_STATE, OSD_EN, AVID)
  begin
      
    case PRESENT_STATE is
    
      when IDLE =>
      -- State machine will idle here till OSD_EN signal goes active
        if OSD_EN = '1'  then
          NEXT_STATE <= INITIAlIZE;
        else
          NEXT_STATE <= IDLE;
        end if;

      when INITIALIZE =>
      -- When OSD functionality has been enabled, the state machine waits till
      -- it detects blanking period.
        if OSD_EN = '1' and AVID = '0' then
          NEXT_STATE <= BLANKING;
        elsif OSD_EN = '0' then
          NEXT_STATE <= IDLE;
        else
          NEXT_STATE <= INITIALIZE;
        end if;
          
      when ACTIVE_VIDEO =>
      -- The state machine goes between Active Video and Blanking states as
      -- long as OSD functionality has been enabled.
        if OSD_EN = '0' then
          NEXT_STATE <= IDLE;
        elsif AVID = '0' then
          NEXT_STATE <= BLANKING;
        else
          NEXT_STATE <= ACTIVE_VIDEO;
        end if;

      when BLANKING =>
      -- The state machine goes between Active Video and Blanking states as
      -- long as OSD functionality has been enabled.
        if OSD_EN = '0' then
          NEXT_STATE <= IDLE;
        elsif AVID = '1' then
          NEXT_STATE <= ACTIVE_VIDEO;
        else
          NEXT_STATE <= BLANKING;
        end if;
    end case;

  end process SM;

  -- purpose: Controls the output based on the state of the state machine
  -- and the various control parameters.  
  MAIN_PROCESS : process(VCLK, RESETz)
  begin
  	if RESETz = '0' or SRESETz = '0' then
 	     	P_EVT_EN <= '0';
   	   	P_MUX_CTL <= VID_DATA;
     	 	P_DATA_UNPACK <= '0';
      		FIFO_FLUSH <= '1';
      		P_FIFO_URUN <= '0';
		L_OSD_XSTART <= (others => '0');
		L_OSD_YSTART <= (others => '0');
		L_OSD_XSTOP <= (others => '1');
		L_OSD_YSTOP <= (others => '1');
		FIELD_SET <= '0';
		FIELD <= '0';
		DETECT_CNTR <= (others => '0');
		CNTR_ON <= '0';
		DETECT_VSYNC <= '0';		
		OSD_START <= '0';
	elsif VCLK'event and VCLK = '1' then

    		P_EVT_EN <= P_EVT_EN;
    		P_MUX_CTL <= P_MUX_CTL;
    		P_DATA_UNPACK <= P_DATA_UNPACK;
    		FIFO_FLUSH <= FIFO_FLUSH;
 		P_FIFO_URUN <= P_FIFO_URUN;
    		L_OSD_XSTART <= L_OSD_XSTART;
    		L_OSD_YSTART <= L_OSD_YSTART;
    		L_OSD_XSTOP <= L_OSD_XSTOP;
    		L_OSD_YSTOP <= L_OSD_YSTOP;	
    		FIELD_SET <= FIELD_SET;
    		FIELD <= FIELD;
    		CNTR_ON <= CNTR_ON;
    		DETECT_CNTR <= DETECT_CNTR;
    		DETECT_VSYNC <= DETECT_VSYNC;
    		OSD_START <= OSD_START;
           
    		case PRESENT_STATE is
            
      			when IDLE =>
      -- This state is reached if OSD functionality has been disabled.
      -- Consequently all DMA events are disabled, the FIFOs are kept flushed,
      -- and the OSD Multiplexer is asked to pass through Video data without
      -- any modifications.
        				P_EVT_EN <= '0';
        				P_MUX_CTL <= VID_DATA;
        				FIFO_FLUSH <= '1';

      			when INITIALIZE =>
      -- Here the FIFO is brought out of reset.  The multiplexer is asked to continue outputting video data
        				P_EVT_EN <= '0';
        				P_MUX_CTL <= VID_DATA;
        				FIFO_FLUSH <= '0';

      			when ACTIVE_VIDEO =>
      
      				if COUNT_EN = '1' then
      -- If OSD_START is set, field detection is complete and the OSD can look at the FL_COUNT and FP_COUNT
      -- to check for OSD window.  If within the window, OSD data will be outputted.
     		
					if (((unsigned(FP_COUNT) >= unsigned(L_OSD_XSTART)) and (unsigned(FP_COUNT) < unsigned(L_OSD_XSTOP + 1))) and
					((unsigned(FL_COUNT) >= unsigned(L_OSD_YSTART)) and (unsigned(FL_COUNT) < unsigned(L_OSD_YSTOP + 1)))) and 
					OSD_START = '1' then		
      -- OSD data can be multiplexed with active video data.  However, if the
      -- OSD data FIFO is empty, the multiplexer is asked to output Video
      -- data.
  						if FIFO_EMPTY = '1' then
	 						P_MUX_CTL <= VID_DATA;
      	  						P_DATA_UNPACK <= '0';
        	  						P_FIFO_URUN <= '1';
       						else
        -- if FIFO is not empty and then OSD multiplexer is asked to look at alpha 
	-- from Unpack module to decide whether to output video or osd data.
          							P_MUX_CTL <= OSD_DATA;
            							P_DATA_UNPACK <= '1';
							P_FIFO_URUN <= '0';
						end if;
					else
						P_MUX_CTL <= VID_DATA;
						P_DATA_UNPACK <= '0';
		
        						if FIFO_EMPTY = '0' then