fifo_monitor.vhd

来自「TI evm642的源码,给那些没有买TI的评估板,却想要评估板程序的人.」· VHDL 代码 · 共 66 行

------------------------------------------------------------------------------
-- *** Disclaimer: This example code is provided with no support. ***
------------------------------------------------------------------------------
-- File          : fifo_monitor.vhd
-- Author        : Shraddha
-- Created       : 
-- Last modified : 02/06/03
-- Project	 : OSD FPGA
------------------------------------------------------------------------------
-- Description : Monitors status of FIFO
-- 
------------------------------------------------------------------------------
-- Modification history :
-- 02/06/03 : Shraddha : created
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity FIFO_MONITOR is
port (
    -- from Power Supply
    RESETz              : in std_logic;  -- System Reset
    
    -- Clock
    VCLK                : in std_logic;  -- 27 Mhz Video Clock

    -- from EMIF interface
    FIFO_WE             : in std_logic;  -- FIFO write enable

    -- from FIFO
    FIFO_EMPTY          : in std_logic;  -- FIFO empty indicator

    -- from unpack
    FIFO_RD             : in std_logic;  -- FIFO read request

    -- To Reg module
    FIFO_URUN           : out std_logic  -- FIFO underrun indicator
    );
end FIFO_MONITOR;

architecture RTL of FIFO_MONITOR is

begin	-- RTL


  -- purpose: checks for FIFO underrun
  URUN: process (VCLK, RESETz)
  begin  -- process URUN
    if RESETz = '0' then                -- asynchronous reset (active low)
      FIFO_URUN <= '0';
    elsif VCLK'event and VCLK = '1' then  -- rising clock edge
      if FIFO_EMPTY = '1' and FIFO_RD = '1' then
          FIFO_URUN <= '1';
      elsif FIFO_WE = '1' then
          FIFO_URUN <= '0';
      end if;
    end if;
  end process URUN;  

end RTL;