osd_clut.vhd

TI evm642的源码,给那些没有买TI的评估板,却想要评估板程序的人.

------------------------------------------------------------------------------
-- *** Disclaimer: This example code is provided with no support. ***
------------------------------------------------------------------------------
-- File          : osd_clut.vhd
-- Author        : Shraddha
-- Created       : 
-- Last modified : Jan 29, 2003
-- Project	 : OSD FPGA
------------------------------------------------------------------------------
-- Description : Color lookup table for OSD.  The CLUT is implemented using
-- RAM memory as a FIFO.  The user can write to it as a FIFO.  To ensure that
-- the FIFO pointers are reset and pointing to the right location, CLEAR_CLUT
-- signal must be asserted at the beginning of the CLUT load.  The CLUT cannot
-- be read back by the DM642.
-- 
------------------------------------------------------------------------------
-- Modification history :
-- Jan 29, 2003 : Shraddha : created
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity OSD_CLUT is
port (
    -- from Power Supply
    RESETz              : in std_logic;  -- System Reset
    SRESETz             : in std_logic;  -- Soft Reset
    
    -- Clock
    EMIF_CLK            : in std_logic;  -- EMIF Clock
    VCLK                : in std_logic;  -- Video Clock
    
    -- From EMIF_IF
    CLUT_DATA_INb       : in std_logic_vector(23 downto 0);  -- CLUT data
    CLUT_WE             : in std_logic;  -- CLUT write enable

    -- from registers
    BUS_WIDTH_8         : in std_logic;  -- Bus width is 8 and not 16
    CLEAR_CLUT          : in std_logic;  -- Clear the CLUT write counters

    -- To OSD_MUX
    CLUT_DATA_OUTb      : out std_logic_vector(15 downto 0);  -- CLUT/OSD Data
    ALPHA_LSB           : out std_logic;
    ALPHA_MSB           : out std_logic;

    -- from Unpack
    CLUT_ADDRb          : in std_logic_vector(6 downto 0);  -- CLUT Address
    CLUT_LOOKUP         : in std_logic;
    ALPHA_IN            : in std_logic
    );
end OSD_CLUT;

architecture RTL of OSD_CLUT is
component ram_128x24
	port (
	addra: IN std_logic_VECTOR(6 downto 0);
	addrb: IN std_logic_VECTOR(6 downto 0);
	clka: IN std_logic;
	clkb: IN std_logic;
	dina: IN std_logic_VECTOR(23 downto 0);
	doutb: OUT std_logic_VECTOR(23 downto 0);
	wea: IN std_logic);
end component;

-- XST black box declaration
attribute box_type : string;
attribute box_type of ram_128x24: component is "black_box";

-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of ram_128x24: component is true;
                                                   

signal WR_ADDRb : std_logic_vector(6 downto 0);
signal CLUT_DATA : std_logic_vector(23 downto 0);  -- Output from the CLUT RAM
signal L1_CLUT_DATA, L2_CLUT_DATA : std_logic_vector(23 downto 0);
signal CLK_COUNT : std_logic_vector(1 downto 0);           -- Counts clocks
signal L1_ALPHA, L2_ALPHA, L3_ALPHA, L4_ALPHA : std_logic;
signal L1_CLUT_LOOKUP : std_logic;
                                                   

begin	-- RTL

  RAM_MODULE : ram_128x24
    port map (
      addra     => WR_ADDRb,
      addrb     => CLUT_ADDRb,
      clka      => EMIF_CLK,
      clkb      => VCLK,
      dina      => CLUT_DATA_INb,
      doutb     => CLUT_DATA,
      wea       => CLUT_WE
      );
  

  -- purpose: generates the Write Address for the CLUT RAM
  WR_ADDR_CTL: process (EMIF_CLK, RESETz)
  begin  -- process WR_ADDR_CTL
    if RESETz = '0' or SRESETz = '0' then                -- asynchronous reset (active low)
      WR_ADDRb <= (others => '0');
    elsif EMIF_CLK'event and EMIF_CLK = '1' then  -- rising clock edge
      -- When CLEAR_CLUT signal is asserted, the WR_ADDRb pointer is reset to
      -- zero. Otherwise, the WR_ADDRb address pointer increments everytime
      -- the CLUT is written into.
      if CLEAR_CLUT = '1' then
        WR_ADDRb <= (others => '0');
      elsif CLUT_WE = '1' then
        WR_ADDRb <= WR_ADDRb + 1;
      else
        WR_ADDRb <= WR_ADDRb;
      end if;
    end if;
  end process WR_ADDR_CTL;

  -- purpose: adds latency to signals
  -- type   : sequential
  LATENCY: process (VCLK, RESETz)
  begin  -- process LATENCY
    if RESETz = '0' or SRESETz = '0' then -- asynchronous reset (active low)
      L1_CLUT_DATA <= ( others => '0');
      L2_CLUT_DATA <= ( others => '0');
      L1_ALPHA  <= '0';
      L2_ALPHA <= '0';
      L3_ALPHA <= '0';
      L4_ALPHA <= '0';
      L1_CLUT_LOOKUP <= '0';
    elsif VCLK'event and VCLK = '1' then  -- rising clock edge
      L1_CLUT_DATA <= CLUT_DATA;
      L2_CLUT_DATA <= L1_CLUT_DATA;
      L1_ALPHA <= ALPHA_IN;
      L2_ALPHA <= L1_ALPHA;
      L3_ALPHA <= L2_ALPHA;
      L4_ALPHA <= L3_ALPHA;
      L1_CLUT_LOOKUP <= CLUT_LOOKUP;
    end if;
  end process LATENCY;

  -- purpose: controls the output sequence of the OSD CLUT.  Output sequence
  -- for 8 bit Video is Cb, Y, Cr, Y.  The CLUT holds Luma (Y) in bits 7
  -- downto 0, Cb in bits 15 downto 8, and Cr in bits 23 downto 16.  The
  -- sequence is Cb0, Y0, Cr0, Y1, Cb2, Y2, Cr2, Y3 . . so on.
  -- For 16 bit Video the Y is output from this module on the lower 8 bits and
  -- the chroma on the upper 8 bits.  The sequence on Y bits is Y0, Y1, Y2 . .
  -- and on chroma bits, Cb0, Cr0, Cb2, Cr2, Cb4, Cr4, . . etc.
  -- The alpha follows the alpha from the pixel data for each luma and chroma
  -- outputs.  i.e. For Cb0,Y0,Cr0 the alpha is taken from pixel P0 from the
  -- Unpack module, for Y1 from P1, for Cb2, Y2, Cr2 from P2 etc.
  -- The CLK_COUNT signal is used to keep track of the sequence.
  CLUT_OUT_CTL : process (VCLK, RESETz)
      
  begin  -- process CLUT_OUT_CTL
      if RESETz = '0' or SRESETz = '0' then
          CLUT_DATA_OUTb <= ( others => '0');
          CLK_COUNT <= "00";
          ALPHA_LSB <= '0';
          ALPHA_MSB <= '0';
      elsif VCLK'event and VCLK = '1' then
          if L1_CLUT_LOOKUP = '1' then
              if BUS_WIDTH_8 = '1' then
                  case CLK_COUNT is
                      when "00" =>
                          CLUT_DATA_OUTb(7 downto 0) <= CLUT_DATA(15 downto 8);
                          ALPHA_LSB <= L1_ALPHA;
                      when "01" =>
                          CLUT_DATA_OUTb(7 downto 0) <= L1_CLUT_DATA(7 downto 0);
                          ALPHA_LSB <= L2_ALPHA;
                      when "10" =>
                          CLUT_DATA_OUTb(7 downto 0) <= L2_CLUT_DATA(23 downto 16);
                          ALPHA_LSB <= L3_ALPHA;
                      when "11" =>
                          CLUT_DATA_OUTb(7 downto 0) <= CLUT_DATA(7 downto 0);
                          ALPHA_LSB <= L1_ALPHA;
                      when  others =>
                          null;
                  end case;
                  CLUT_DATA_OUTb(15 downto 8) <= ( others => '0');
                  ALPHA_MSB <= '0';
              else
                  CLUT_DATA_OUTb(7 downto 0) <= CLUT_DATA(7 downto 0);
                  ALPHA_LSB <= L1_ALPHA;
                  if CLK_COUNT(0) = '0' then
                      CLUT_DATA_OUTb(15 downto 8) <= CLUT_DATA(15 downto 8);
                      ALPHA_MSB <= L1_ALPHA;
                  else
                      CLUT_DATA_OUTb(15 downto 8) <= L1_CLUT_DATA(23 downto 16);
                      ALPHA_MSB <= L2_ALPHA;
                  end if;
              end if;
              CLK_COUNT <= CLK_COUNT + 1;
          else
              CLK_COUNT <= "00";
          end if;
      end if;
  end process CLUT_OUT_CTL;

  
end RTL;